• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.259-268
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• 2008

Multi-Core processors have become main-stream microprocessors in recent years. Servers based on these multi-core processors are widely adopted in High Performance Computing (HPC) and commercial business applications as well. These servers provide increased level of parallelism, thus can potentially boost the performance for applications. However, the shared resources among multiple cores on the same chip can become hot spots and act as performance bottlenecks. Therefore it is essential to optimize the use of shared resources for high performance and scalability for the multi-core servers. In this paper, we conduct experimental studies to analyze the positive and negative effects of the resource sharing on the performance of HPC applications. Through the analyses we also characterize the performance of multi-core servers.

• Journal of Korea Multimedia Society
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• v.18 no.6
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• pp.723-733
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• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• The Journal of Korean Institute for Practical Engineering Education
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• v.3 no.1
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• pp.25-31
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• 2011

These days, almost all of the embedded systems have microprocessors or micro-controllers in them as their brains. So microprocessor related subjects become very important and most engineering departments have those kinds of subjects in their curriculums with practice hours. However, in most universities in Korea, the number of students in a class is more than 40 and only one teaching assistant is assigned to the class. So it is very hard job to find out an appropriate method to evaluate the students' achievements in their practice hours fairly. In this study, the author introduces some suggestions for the evaluation of the students' achievements in microprocessor practice courses. In addition to it, the author also introduces some guidelines for contents of microprocessor related subjects.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.