• Archives of design research
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• v.19 no.3 s.65
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• pp.93-104
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• 2006

When the design profession started, design targets were mainly static hardware centered products. Due to the development of network and digital technologies, new products with dynamic and software-hardware hybrid interactive characteristics have become one of the main design targets. To accomplish the new projects, designers are required to learn new methods, tools and theories in addition to the traditional design expertise of visual language. One of the most important tools for the change is effective and rapid prototyping. There have been few researches on educational framework for interactive product or system prototyping to date. This paper presents a new model of educational contents and methods for interactive digital product prototyping, and it's application in a design curricula. The new course contents, integrated with related topics such as physical computing and tangible user interface, include microprocessor programming, digital analogue input and output, multimedia authoring and programming language, sensors, communication with other external devices, computer vision, and movement control using motors. The final project of the course was accomplished by integrating all the exercises. Our educational experience showed that design students with little engineering background could learn various interactive digital technologies and its' implementation method in one semester course. At the end of the course, most of the students were able to construct prototypes that illustrate interactive digital product concepts. It was found that training for logical and analytical thinking is necessary in design education. The paper highlights the emerging contents in design education to cope with the new design paradigm. It also suggests an alterative to reflect the new requirements focused on interactive product or system design projects. The tools and methods suggested can also be beneficial to students, educators, and designers working in digital industries.

• Journal of Digital Contents Society
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• v.18 no.5
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• pp.881-888
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• 2017

Logic design using multiplexer has been used as a useful method for design convenience and flexibility in structural digital system design. In this paper, we analyze the effect of don't care conditions on logic optimization in a multiplexer-based logic design, which was not discussed enough in the previous studies in multiplexer based logic design, and describe the use of don't care conditions for designing of a single multiplexer and multiple multiplexer-based logic design. Especially, the design method when the number of data input is not 2m (as the number of selection lines is m) is considered. We also describe how to apply the proposed technique to the digital logic design education in conjunction with microprocessor design using Arduino which is widely used in creative engineering education recently.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.143-148
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• 2020

In the case of a system that detects and controls the phase of an alternating voltage, the analog control method compensates the phase offset part by filtering for the detected phase and applies it to the control. However, in the digital control method, precise control cannot be achieved due to an error between the operating frequency of the microprocessor or the microcontroller and the input phase time when controlled using such phase detection. In general, when the method used is a certain time, the accumulated error is compensated and adjusted at random. To solve this problem, a method of detecting a zero point in real time and compensating for the operating frequency of the microprocessor is needed. Therefore, the research to be performed in this paper to reduce these errors and apply them to precise digital control is as follows. 1) Research on how to implement Zero Crossing Detection algorithm through simulation modeling to compensate the zero point to match the operating frequency through detection. 2) A study on the method of detecting zero points in real time through the Zero Crossing Detection design using a microcontroller and compensating for the operating frequency of the microprocessor. 3) A study on the estimation of the rotor position of BLDC motors using the Zero Crossing Detection circuit.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.974-984
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• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.763-773
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• 2003

In this paper, we present a register renaming method for conditional execution out-of-order instruction issue microprocessors. Register renaming method reduces false data dependencies (write after read(WAR) and write after write(WAW)). To implement a conditional execution out-of-order instruction issue microprocessor using register renaming, we use a register file which includes both in-order state physical registers and look-ahead state physical registers to share all logical registers. And we design an in-order state indicator, a renaming state indicator, a physical register assigning indicator, a condition prediction buffer and a reorder buffer. As we utilize the above hardwares, we can do register renaming and trace the in-order state. In this paper, we present an improved register renaming method using smaller hardware resources than conventional register renaming method. And this method eliminates an associative lookup and provides a short recovery time.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.364-370
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• 2002

A banknote counter is a machine that automates counting the money in some agencies to treat much banknotes as well as general banking agencies. The banknote counter materialized in this paper is the machine that adds the function of banknote sorting, detecting plural banknote and detecting counterfeit banknote to an existing banknote counter. The technique of sensor signal processing are used for banknote sorting. The technique of sensor application and data processing are used for detecting counterfeit banknote. The technique of precision equipment design and microprocessor application are used for high speed count. Software improved in debugging and difficulties to link with additional hardware. It was materialized through effective control algorithm and real-time signal processing with C-language on the basis of RTOS(real-time operating system) Photodiode, its applications and a magnetic resistance sensor are used as a sensor device with regard to hardware cost -cutting and process velocity. PCF80C552-24 of Philips using Intel I8051 core is used as a control microprocessor. As the results so far achieved, counterfeit banknotes made by the use of a color duplicator and a color Printer, are distinguished from real banknotes through mixing an optical with a magnetic sensor. and, in case that there are some different banknotes while counting, it is prevented for them to be counted without discriminating from the same kind of banknotes in addition to the fu notion of banknote sorting.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.1
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• pp.50-56
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• 2008

In this paper, a digital inclinometer to measure the angle and acceleration signals of subject laid on Roll was designed. The designed system consists of a tilt sensor, biaxial accelerometer, single chip microprocessor and Bluetooth module. The designed digital inclinometer was easy to handle and to wear. To evaluate the performance of the system, we measured simultaneously the angle and acceleration signals from the 3 subjects on the Roll using two instruments which are ZEBRIS and designed system. The measured signals were processed by statistical method and then the correlation coefficient of 0.93 was shown. From the results, the designed digital inclinometer is shown to be useful in assessment of body movement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.19-24
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• 2008

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.