• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.177-183
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• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.72-83
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• 2002

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

• Journal of the Korean Society of Industry Convergence
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• v.18 no.4
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• pp.250-258
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• 2015

In this research, we proposed a new approach to implement the real-time motion control of biped robot based on voice command for unmanned FA. Voice is one of convenient methods to communicate between human and robots. To command a lot of robot task by voice, voice of the same number have to be able to be recognition voice is, the higher the time of recognition is. In this paper, a practical voice recognition system which can recognition a lot of task commands is proposed. The proposed system consists of a general purpose microprocessor and a useful voice recognition processor which can recognize a limited number of voice patterns. Given biped robots, each robot task is, classified and organized such that the number of robot tasks under each directory is net more than the maximum recognition number of the voice recognition processor so that robot tasks under each directory can be distinguished by the voice recognition command. By simulation and experiment, it was illustrated the reliability of voice recognition rates for application of the manufacturing process.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.364-370
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• 2002

A banknote counter is a machine that automates counting the money in some agencies to treat much banknotes as well as general banking agencies. The banknote counter materialized in this paper is the machine that adds the function of banknote sorting, detecting plural banknote and detecting counterfeit banknote to an existing banknote counter. The technique of sensor signal processing are used for banknote sorting. The technique of sensor application and data processing are used for detecting counterfeit banknote. The technique of precision equipment design and microprocessor application are used for high speed count. Software improved in debugging and difficulties to link with additional hardware. It was materialized through effective control algorithm and real-time signal processing with C-language on the basis of RTOS(real-time operating system) Photodiode, its applications and a magnetic resistance sensor are used as a sensor device with regard to hardware cost -cutting and process velocity. PCF80C552-24 of Philips using Intel I8051 core is used as a control microprocessor. As the results so far achieved, counterfeit banknotes made by the use of a color duplicator and a color Printer, are distinguished from real banknotes through mixing an optical with a magnetic sensor. and, in case that there are some different banknotes while counting, it is prevented for them to be counted without discriminating from the same kind of banknotes in addition to the fu notion of banknote sorting.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.35-45
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• 2011

The Salsa20/12 stream cipher selected for the final eSTREAM portfolio has a better performance than software implementation of AES using an 8-bit microprocessor with restricted memory space, In the theoretical approach, the evaluation of exploitable timing vulnerability was 'none' and the complexity of side-channel analysis was 'low', but there is no literature of the practical result of power analysis attack. Thus we propose the correlation power analysis attack method and prove the feasibility of our proposed method by practical experiments, We used an 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement Salsa20/12 stream cipher without any countermeasures, and performed the experiments of power analysis based on Hamming weight model.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.12
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• pp.1036-1040
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• 2002

To process data of digital linescan camera, the frame grabber is essential to handle the data in low-level and in high speed more than 30 MHz stably. Traditional approaches to the development of hardware in vision system for the special purpose are mai y based on PC system, and are expensive and gigantic. Therefore, there are many difficulties in applying those in the field. So we investigate, in this paper, the implementation of FPGA for real-time processing of digital linescan camera. The system is not based on PC, but electronic device such as micropncessor. So it is expected that the use of FPGAs for low-level processing represents a fast, stable and inexpensive system. The experiments are carried out on the web guiding system in order to show the efficiency of the new image processor.