• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.855-858
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• 2011

In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-$SrTiO_3$) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.

• Journal of Hydrogen and New Energy
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• v.3 no.2
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• pp.17-24
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• 1992

Hydrogen gas sensors were fabricated after the form of metal/insulator/semiconductor(MIS) structure on a p-type silicon wafer and a insulating layer (silicon dioxide) thickness was changed from $500{\AA}$ to $5000{\AA}$. Their electrical properties were investigated with the variation of the hydrogen gas concentration at room temperature. At the applied forward bias of lV to both ends of Pd-MIS sensors the current was decreased logarithmically with the increase of hydrogen concentration in air. In the case of a thin $SiO_2$ layered ($500{\AA}$) sensor the current ratio was decreased to 25 % at 1 % of hydrogen concentration in air and 50% for a thick $SiO_2$ layered ($5000{\AA}$) sensor. And the response time of the thick insulating layered sensor to 1% hydrogen containing air was about 50 seconds and regeneration time was 2.5 minutes. When a 0.5mA current was appied to the thick insulating layered sensor the maximun voltage shift was calculated to 0.8V in the case of ${\theta}$ = 1 and the Pd surface coverage of hydrogen was increased logarithmically with hydrogen partial pressure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.383-387
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• 2002

N-channel metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFISFET's) by using $SrBi_2Ta_2O_9$/Silicon Nitride/Si (100) structure were fabricated. The fabricated devices exhibit comfortable memory windows, fast switching speeds, good fatigue resistances, and long retention times that are suitable for advanced ferroelectric memory applications. The estimated switching time and polarization ($2P_r$) of the fabricated FET measured at applied electric field of 376 kV/cm were less than 50 ns and about 1.5 uC/$\textrm{cm}^2$, respectively. The magnitude of on/off ratio indicating the stored information performance was maintained more than 3 orders until 3 days at room temperature. The $I_DV_G$ characteristics before and after being subjected to $10^11$ cycles of fatigue at a frequency of 1 MHz remained almost the same except a little distortion in off state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.7-8
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.67-67
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• 2000

CeO2는 cubic 구조의 일종인 CaR2 구조를 가지고 있으며 격자상수가 Si의 격장상수와 매우 비슷하여 Si 기판위에 에피텍셜하게 성장할 수 있는 가능성이 매우 크다. 따라서 SOI(silicon-on-insulator)구조의 실현을 위하여 Si 기판위에 CeO2 박막을 에피텍셜하게 성장시키려는 많은 노력이 있어왔다. 또한 metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이의 완충층으로 사용된다. 이러한 CeO2의 응용을 위해서는 Si 기판 위에 성장된 CeO2 박막의 방위성 및 CeO2/Si 구조의 전기적 특성을 알아보는 것이 매우 중요하다. 본 연구에서는 Si(100) 기판위에 CeO2(200)방향으로 성장하는 박막과 EcO2(111) 방향으로 성장하는 박막을 rf magnetron sputtering 방법으로 증착하여 각각의 구조적, 전기적 특성을 분석하였다. RCA 방법으로 세정한 P-type Si(100)기판위에 Ce target과 O2를 사용하여 CeO2(200) 및 CeO2(111)박막을 증착하였다. 증착후 RTA(rapid thermal annealing)방법으로 95$0^{\circ}C$, O2 분위기에서 5분간 열처리를 하였다 이렇게 제작된 CeO2 박막의 구조적 특성을 XRD(x-ray diffraction)방법으로 분석하였고, Al/CeO2/Si의 MIS(metal-insulator-semiconductor)구조를 제작하여 C-V (capacitance-voltage), I-V (current-voltage) 특성을 분석하였으며 TEM(transmission electron microscopy)으로 증착된 CeO2막과 Si 기판과의 계면 특성을 연구하였다. C-V특성에 있어서 CeO2(111)/Si은 CeO2(111)의 두께가 증가함에 따라 hysteresis windows가 증가한 방면 CeO2(200)/Si은 hysteresis windows가 아주 작을뿐만 아니라 CeO2(200)의 두께가 증가하더라도 hysteresis windos가 증가하지 않았다. CeO2(111)/Si과 CeO2(200)/Si의 C-V 특성의 차이는 CeO2(111)과 CeO2(200)이 Si 기판에 의해 받은 stress의 차이와 이에 따른 defect형성의 차이에 의한 것으로 사료된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.