• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.9-18
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• 2005

60 nm C-MOSFET 기술 분기점 이상의 고성능, 저전력 트랜지스터를 구현 시키기 위해 SiGe/SiO2/Si위에 성장된 strained Si의 두께가 전자 이동도에 미치는 영향을 두 가지 관점에서 조사 연구하였다. 첫째, inter-valley phonon 산란 모델의 매개변수들을 최적화하였고 둘째, strained Si 반전층의 2-fold와 4-fold의 전자상태, 에너지 밴드 다이어그램, 전자 점유도, 전자농도, phonon 산란율과 phonon-limited 전자이동도를 이론적으로 계산하였다. SGOI n-MOSFET의 전자이동도는 고찰된 SOI 구조의 Si 두께 모든 영역에서 일반적인 SOI n-MOSFET보다 $1.5\~1.7$배가 높음이 관찰 되었다. 이러한 경향은 실험 결과와 상당히 일치한다. 특히 strained Si의 두께가 10 nm 이하일 때 Si 채널 두께가 6 nm 보다 작은 SGOI n-MOSFET에서의 phonon-limited 전자 이동도는 일반 SOI n-MOSFET과 크게 달랐다. 우리는 이러한 차이가 전자들이 suained SGOI n-MOSFET의 반전층에서 SiGe층으로 터널링 했기 때문이고, 반면에 일반 SOI n-MOSFET에서는 캐리어 confinement 현상이 발생했기 때문인 것으로 해석하였다. 또한 우리는 10 nm와 3 nm 사이의 Si 두께에서는 SGOI n-MOSFET의 phonon-limited 전자 이동도가 inter-valley phonon 산란율에 영향을 받는 다는 것을 확인하였으며, 이러한 결과는 더욱 높은 드레인 전류를 얻기 위해서 15 nm 미만의 채널길이를 가진 완전공핍 C-MOSFET는 stained Si SGOI 구조로 제작하여야 함을 확인 했다

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.11-16
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• 2002

본 연구에서는 $SrBi_2Ta_2O_9$ (SBT)박막의 고속식각에 따른 잔류물질 및 식각 손상의 영향을 조사하였다. ICP-RIE (inductively coupled plasma reactive ion etching) 의 ICP power와 CCP(capacitively coupled plasma) power를 변화시키면서 고속식각에 따른 박막의 손상과 열화를 XPS 분석과 Capacitance-Voltage (C-V) 측정을 통하여 알아보았다. ICP와 CCP의 power가 증가함에 따라 식각율이 증가하였고 ICP power가 700 W, CCP power가 200 W 일때 식각율은 900$\AA$/min이었다. 강유전체의 건식식각에 있어서 문제점이 플라즈마에 의한 강유전체 박막의 열화인데 반응가스 $Ar/C1_2/CHF_3$를 20/14/2의 비율로 사용하고 ICP와 CCP power를 각각 700w와 200w로 사용하였을 때 전혀 열화되지 않는 강유전체 박막의 특성을 얻을 수 있었다. 본 연구 결과는 Metal-Ferroelectric-Semiconductor (MFS) 또는 Metal-Ferroelectric-Insulator-Semiconductor (MFIS) 구조를 가지는 단일 트랜지스터형 강유전체 메모리 소자를 만드는데 건식 식각이 응용될 수 있음을 보여준다

• 한국재료학회지
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• 제10권3호
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• pp.199-203
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• 2000

세라믹 타겟인 Ta$_2$O(sub)5을 장착한 rf-마그네트론 스퍼터를 이용하여 Ta$_2$O(sub)5 완충층을 증착하고, Sr(sub)0.8Bi(sub)2.4Ta$_2$O(sbu)9 용액을 사용하여 MOD 법에 의해 SBT 막을 성장시킨 metal/ferroelectric/insulator/semiconductor (MFIS) 구조인 Pt/SBT/Ta$_2$O(sub)5/Si 구조의 Ta$_2$O(sub)5 완충층 증착시의 $O_2$유량비, Ta$_2$O(sub)5 완충층 두께에 따른 전기적 특성을 조사하였다. 그리고 Ta$_2$O(sub)5 박막의 완충층으로써의 효과를 확인하기 위해 Pt/SBT/Ta$_2$O(sub)5/Si 구조와 Pt/SBT/Si 구조의 전기적 특성을 비교하였다. Ta$_2$O(sub)5 완충층 증착시의 $O_2$유량비가 0%일 때는 전형적인 MFIS 구조의 C-V 특성을 얻지 못하였으며, 20%의 $O_2$유량비일 때 가장 큰 메모리 윈도우 값을 얻었다. 그리고 $O_2$유량비가 40%, 60%로 증가할수록 메모리 윈도우는 감소하였다. Ta$_2$O(sub)5 완충층의 두께의 변화에 대한 C-V 특성에서는 36nm의 Ta$_2$O(sub)5 두께에서 가장 큰 메모리 값을 얻었다. Pt/SBT/Si 구조의 메모리 윈도우 값과 누설전류 특성은 Pt/SBT/Ta$_2$O(sub)5/Si 구조의 값에 비해 크게 떨어졌으며, 따라서 Ta$_2$O(sub)5 막이 우수한 완충층으로써의 역할을 함을 알았다.

• 대한전자공학회논문지TC
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• 제47권8호
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• pp.61-67
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• 2010

일반적으로 MIS(도체-부도체-반도체)의 다층 구조로 이루어진 대칭 결합선로에 대한 해석 절차는 모드(even and odd) 해석에 기초한 특성임피던스와 전파상수를 추출함으로서 단층의 결합선로 해석 절차와 동일하다. 본 논문에서는 손실매질의 다층구조로 이루어진 마이크로 스트립선로의 손실특성의 개선을 위한 새로운 구조를 제안한다. MIS 구조로 된 전송선로의 Si와 SiO2층 사이에 0전위를 가진 도체를 일정한 간격의 주기적인 배열로 고안된 새로운 모델의 MIS구조에 대한 유한차분법을 이용한 해석방법이 사용된다. 특히 전송선로에 대한 유전체의 영향을 줄이기 위하여 0전위를 가진 주기적인 결합의 도체로 이루어진 구조가 시간영역의 신호를 통해 시험된다. 다양한 손실률을 가진 불완전 유전체에 따른 주파수 의존적인 추출된 전송선로 파라미터와 등가회로 파라미터가 주파수 함수로서 나타내진다. 특히 본 논문에서 제안한 새로운 구조의 불완전 유전체에 대한 전송선로 파라미터가 주파수 함수로 구해진다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.128.1-128.1
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• 2016

Nitrided-metal gates on the high-${\kappa}$ dielectric material are widely studied because of their use for sub-20nm semiconductor devices and the academic interest for the evanescent states at the Si/insulator interface. Issues in these systems with the Si substrate are the electron mobility degradation and the reliability problems caused from N defects that permeates between the Si and the $SiO_2$ buffer layer interface from the nitrided-gate during the gate deposition process. Previous studies proposed the N defect structures with the gap states at the Si band gap region. However, recent experimental data shows the possibility of the most stable structure without any N defect state between the bulk Si valence band maximum (VBM) and conduction band minimum (CBM). In this talk, we present a new type of the N defect structure and the electronic structure of the proposed structure by using the first-principles calculation. We find that the pair structure of N atoms at the $Si/SiO_2$ interface has the lowest energy among the structures considered. In the electronic structure, the N pair changes the eigenvalue of the silicon-induced gap state (SIGS) that is spatially localized at the interface and energetically located just above the bulk VBM. With increase of the number of N defects, the SIGS gradually disappears in the bulk Si gap region, as a result, the system gap is increased by the N defect. We find that the SIGS shift with the N defect mainly originates from the change of the kinetic energy part of the eigenstate by the reduction of the SIGS modulation for the incorporated N defect.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.

• E2M - 전기 전자와 첨단 소재
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• 제9권5호
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• pp.463-469
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• 1996

The double insulating layer consisting of anodic oxide and ZnS was formed for HgCdTe metal insulator semiconductor(MIS) structure. ZnS was evaporated on the anodic oxide grown in H$_{2}$O$_{2}$ electrolyte. Recently, this insulating mechanism for HgCdTe MIS has been deeply studied for improving HgCdTe surface passivation. It was found through TEM observation that an interface layer is formed between ZnS and anodic oxide layers for the first time in the study of this area. EDS analysis of chemical compositions using by electron beam of 20.angs. in diameter and XPS depth composition profile indicated strongly that the new interface is composed of ZnO. Also TEM high resolution image showed that the structure of oxide layer has been changed from the amorphous state to the microsrystalline structure of 100.angs. in diameter after the evaporation of ZnS. The double insulating layer with the resistivity of 10$^{10}$ .ohm.cm was estimated to be proper insulating layer of HgCdTe MIS device. The optical reflectance of about 7% in the region of 5.mu.m showed anti-reflection effect of the insulating layer. The measured C-V curve showed the large shoft of flat band voltage due to the high density of fixed oxide charges about 1.2*10$^{12}$ /cm$^{2}$. The oxygen vacancies and possible cationic state of Zn in the anodic oxide layer are estimated to cause this high density of fixed oxide charges.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.172-173
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• 2006

Metal-ferroelectric-insulator-semiconductor (MFIS) structures with $Bi_{3.35}La_{0.75}Ti_3O_{12}$ (BLT) ferroelectric film and Zirconium oxide ($ZrO_2$) layer were fabricated on p-type Si(100). $ZrO_2$ and BLT films were prepared by sol-gel technique. Surface morphologies of $ZrO_2$ and BLT film were measured by atomic force microscope (AFM). The electrical characteristics of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si film were investigated by C-V and I-V measurements. No hysteretic characteristics was observed in the C-V curve of the Au/$ZrO_2$/Si structure. The memory window width m C-V curve of the Au/BLT/$ZrO_2$/Si diode was about 1.3 V for a voltage sweep of ${\pm}5$ V. The leakage current of Au/$ZrO_2$/Si and Au/BLT/$ZrO_2$/Si structures were about $3{\times}10^{-8}$ A at 30 MV/cm and $3{\times}10^{-8}$ A at 3 MV/cm, respectively.

• 한국전기전자재료학회논문지
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• 제22권4호
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• pp.350-354
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• 2009

$Al_{2}O_{3}$ thin films were deposited on GaN(0001) by using a Remote Plasma Atomic Layer Deposition(RPALD) technique with a trimethylaluminum(TMA) precursor and oxygen radicals in the temperature range of $25{\sim}500^{\circ}C$. The growth rate per cycle was varied with the substrate temperature from $1.8{\AA}$/cycle at $25^{\circ}C$ to $0.8{\AA}$/cycle at $500^{\circ}C$. The chemical structure of the $Al_{2}O_{3}$ thin films was studied using X-ray photoelectron spectroscopy(XPS). The electrical properties of $Al_{2}O_{3}$/GaN Metal-Insulator-Semiconductor (MIS) capacitor grown at a $300^{\circ}C$ process temperature were excellent, a low electrical leakage current density(${\sim}10^{-10}A/cm^2$ at 1 MV) at room temperature and a high dielectric constant of about 7.2 with a thinner oxide thickness of 12 nm. The interface trap density($D_{it}$) was estimated using a high-frequency C-V method measured at $300^{\circ}C$. These results show that the RPALD technique is an excellent choice for depositing high-quality $Al_{2}O_{3}$ as a Sate dielectric in GaN-based devices.