• 제목/요약/키워드: Metal oxide semiconductor

검색결과 715건 처리시간 0.025초

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

  • Kim, Yong-Bin
    • Transactions on Electrical and Electronic Materials
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    • 제12권5호
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    • pp.175-188
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    • 2011
  • As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

MOSFET에서 다결정 실리콘 게이트 막의 도핑 농도가 신뢰성에 미치는 영향 (Effects of Doping Concentration of Polycrystalline Silicon Gate Layer on Reliability Characteristics in MOSFET's)

  • 박근형
    • 한국전기전자재료학회논문지
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    • 제31권2호
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    • pp.74-79
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    • 2018
  • In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

확장성을 고려한 QCA XOR 게이트 설계 (Design of Extendable XOR Gate Using Quantum-Dot Cellular Automata)

  • 유영원;김기원;전준철
    • 한국항행학회논문지
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    • 제20권6호
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    • pp.631-637
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    • 2016
  • CMOS (complementary metal-oxide-semiconductor)의 소형화에 대한 한계를 극복할 수 있는 대체 기술 중 하나인 양자 셀룰라 오토마타 (QCA; quantum cellular automata)는 나노 단위의 셀들로 이루어져 있고, 전력의 소모량이 매우 적은 것이 특징이다. QCA를 이용한 다양한 회로들이 연구되고 있고, 그 중에서 XOR (exclusive-OR)게이트는 오류 검사 및 복구에 유용하게 사용되고 있다. 기존의 XOR 논리 게이트는 확장성이 부족하고, 클럭 구간의 수가 많이 소요되며, 실제 구현에 어려움이 있는 경우가 많다. 이러한 단점을 극복하기 위해 클럭 구간의 수를 단축한 다수결 게이트를 이용한 XOR 논리 게이트를 제안한다. 제안한 회로는 기존의 XOR 논리 게이트들과 비교 분석하고 그 성능을 검증한다.

비휘발성 메모리를 위한 $SiO_2/Si_3N_4$ 적층 구조를 갖는 터널링 절연막의 열처리 효과 (Annealing Effects of Tunneling Dielectrics Stacked $SiO_2/Si_3N_4$ Layers for Non-volatile Memory)

  • 김민수;정명호;김관수;박군호;정종완;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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    • pp.128-129
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    • 2008
  • The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

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Oxidized-SiN으로 형성된 4H-SiC MOS capacitor.의 전기적 특성 (Electrical properties of Metal-Oxide-Semiconductor (MOS) capacitor formed by oxidized-SiN)

  • 문정헌;김창현;이도현;방욱;김남균;김형준
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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    • pp.45-46
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    • 2009
  • We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with thin (${\approx}10\;nm$) Inductive-Coupled Plasma (ICP) CVD $Si_xN_y$ dielectric layers and investigated electrical properties of nitrided $SiO_2$/4H-SiC interface after oxidizing the $Si_xN_y$ in dry oxidation and/or $N_2$ annealing. An improvement of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements if compared with non-annealed oxidized-SiN. The improvements of SiC MOS capacitors formed by oxidized-SiN have been explained in this paper.

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Preparation of Epoxy/Organoclay Nanocomposites for Electrical Insulating Material Using an Ultrasonicator

  • Park, Jae-Jun;Park, Young-Bum;Lee, Jae-Young
    • Transactions on Electrical and Electronic Materials
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    • 제12권3호
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    • pp.93-97
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    • 2011
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

온도변화에 따른 LDMOS의 전류변동 억제에 관한 연구 (A Study of Suppression Current for LDMOS under Variation of Temperature)

  • 전중성
    • Journal of Advanced Marine Engineering and Technology
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    • 제30권8호
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    • pp.901-906
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    • 2006
  • In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

원자층 증착 방법에 의한 $Ta_2O_5$ 박막의 전기적 특성 (The Electrical Properties of $Ta_2O_5$ Thin Films by Atomic Layer Deposition Method)

  • 이형석;장진민;장용운;이승봉;문병무
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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    • pp.41-46
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    • 2002
  • In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

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폐수의 악취측정을 위한 금속산화물 반도체 및 전기화학식 가스센서 어레이 특성 평가 (Evaluation of Metal Oxide Semiconductor and Electrochemical Gas Sensor Array Characterization for Measuring Wastewater Odor)

  • 임봉빈;이석준;김선태
    • 센서학회지
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    • 제24권1호
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    • pp.29-34
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    • 2015
  • This study aimed to evaluate the characterization of a metal oxide semiconductor and electrochemical gas sensor array for measuring wastewater odor. The sensitivity of all gas sensors observed in sampling method by stripping was 6.7 to 20.6 times higher than that by no stripping, except sensor D (electrochemical gas sensor). The average reduction ratio of sensor signal as a function of initial dilution rate of wastewater was in the order of food plant > food waste reutilization facility > plating plant. The sensitivity of gas sensors was dependent on both the type of wastewater and the dilution rate. The sensor signals observed by the gas sensor array were correlated with the dilution factor (OU) calculated by the air dilution sensory test with several wastewater ($r^2=0.920{\sim}0.997$), except the sensor signals of sensor D measured in the plating plant wastewater. It seems likely that the gas sensor array plays a role in the evaluation of odor in wastewater and is useful tool for on-site odor monitoring in the wastewater facilities.

전압모드 PWM DC/DC 전력 컨버터 설계연구 (A Study on the Design of Voltage Mode PWM DC/DC Power Converter)

  • 노영환
    • 한국철도학회논문집
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    • 제14권5호
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    • pp.411-415
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    • 2011
  • DC/DC컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 전력변환기이다. 전압모드 DC/DC 컨버터는 주기적으로 입력측에서 출력측으로 전달되는 에너지를 제어하는 기능을 수행하기 위해 MOSFET(산화물-반도체 전계 효과 트랜지스터), 인덕터, PWM 제어기(오실레이터, 연산증폭기, 비교기로 구성)를 이용한다. 본 논문에서 PWM(펄스폭 변조) 모듈과 스위칭모드로 제어하는 기본적인 승압과 강압컨버터를 연구하고, 전기적 특성을 SPICE로 시뮬레이션을 수행하며, 전력의 효율을 각 소자의 변화와 사양에 따라 분석하는데 있다.