• Title/Summary/Keyword: Metal oxide material

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Synthesis of LiCoO2 Powders using Recycled Cobalt Precursors from Waste WC-Co Hard Metal (폐 WC-Co계 초경합금에서 추출된 코발트 재생 원료를 이용한 LiCoO2 입자 합성 연구)

  • Yang, Hee-Seung;Pee, Jae-Hwan;Kim, Yoo-Jin
    • Journal of Powder Materials
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    • v.18 no.3
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    • pp.277-282
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    • 2011
  • [ $LiCoO_2$ ] a cathode material for lithium rechargeable batteries, was prepared using recycled $Co_3O_4$. First, the cobalt hydroxide powders were separated from waste WC-Co hard metal with acid-base chemical treatment, and then the impurities were eliminated by centrifuge method. Subsequently, $Co_3O_4$ powders were prepared by thermal treatment of resulting $Co(OH)_2$. By adding a certain amount of $Li_2CO_3$ and $LiOH{\cdot}H_2O$, the $LiCoO_2$ was obtained by sintering for 10 h in air at $800^{\circ}C$. The synthesized $LiCoO_2$ particles were characterized by X-ray diffraction (XRD) and Scanning Electron Microscope (SEM) analysis.

Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

  • Baek, Ki-Ju;Kim, Jun-Kyu;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.15-19
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    • 2010
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

Synthesis of CoO/Co(OH)2 Nanosheets Depending on Reaction Temperatures (반응 온도에 따른 CoO/Co(OH)2 나노시트의 합성)

  • Minjeong Lee;Gayoung Yoon;Gyeong Hee Ryu
    • Korean Journal of Materials Research
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    • v.33 no.5
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    • pp.222-228
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    • 2023
  • Transition metal oxides formed by a single or heterogeneous combination of transition metal ions and oxygen ions have various types of crystal structures, which can be classified as layered structures and non-layered structures. With non-layered structures, it is difficult to realize a two-dimensional structure using conventional synthesis methods. In this study, we report the synthesis of cobalt oxide into wafer-scale nanosheets using a surfactant-assisted method. A monolayer of ionized surfactant at the water-air interface acts as a flexible template for direct cobalt oxide crystallization below. The nanosheets synthesized on the water surface can be easily transferred to an arbitrary substrate. In addition, the synthesizing morphological and crystal structures of the nanosheets were analyzed according to the reaction temperatures. The electrochemical properties of the synthesized nanosheets were also measured at each temperature. The nanosheets synthesized at 70 ℃ exhibited higher catalytic properties for the oxygen evolution reaction than those synthesized at other temperatures. This work suggests the possibility of changing material performance by adjusting synthesis temperature when synthesizing 2D nanomaterials using a wide range of functional oxides, resulting in improved physical properties.

A Study of the Electrical Characteristics of WOx Material for Non-Volatile Resistive Random Access Memory (비-휘발성 저항 변화 메모리 응용을 위한 WOx 물질의 전기적 특성 연구)

  • Jung, Kyun Ho;Kim, Kyong Min;Song, Seung Gon;Park, Yun Sun;Park, Kyoung Wan;Sok, Jung Hyun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.5
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    • pp.268-273
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    • 2016
  • In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

Effect of Uderpass Structure on Quality Factor and Breakdown Voltage in RF Inductor (RF 인덕터의 Underpass에 따른 품질 계수 및 항복전압 특성)

  • Shin, Jong-Kwan;Kwon, Sung-Kyu;Jang, Sung-Yong;Jung, Jin-Woong;Yu, Jae-Nam;Oh, Sun-Ho;Kim, Choul-Young;Lee, Ga-Won;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.6
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    • pp.356-360
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    • 2014
  • In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.

Design and Analysis of AlN Piezoelectric Micro Energy Harvester Based on Vibration (AlN 압전 진동형 마이크로 에너지 하베스터 설계 및 분석)

  • Lee, Byung-Chul;Chung, Gwiy-Sang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.5
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    • pp.424-428
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    • 2010
  • This paper describes the design and analysis of AlN piezoelectric micro energy harvester. The harvester was designed to convert ambient vibration energy to electrical power as a AlN piezoelectric material compatible with CMOS (complementary metal oxide semiconductor) process. To cut off the leakage current, AlN was used as the insulating layer. Also, Mo was used for the excellent c-axis crystal growth as the bottom electrode. The AlN harvester which it has the low operating frequency was designed by using the ANSYS FEA (finite element analysis). From the simulation results, the resonance frequency of designed model is about 360 Hz and analyzed the bending mode, displacement and expectation output.

Peculiarities of amorphous and crystalline dielectric films prepared by sol-gel method

  • Natalya, Korobova;Soh, Dea-Wha
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.401-402
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    • 2005
  • The important parts of material science in the film preparation fields and sol-gel technology are presented. For the present work, a series of amorphous films was prepared in air by sol-gel method without using some alkoxide stabilizer, which reduces the reactivity of the metal alkoxides. The choice of precursors can affect the chemical-reaction kinetics, microstructures and properties of the product. In this report author compared the crystallization behavior of oxide functional films derived from the same precursors, stressing the influence of experiment conditions and where it was possible to obtain the uniform amorphous or crystalline dielectric films. A short analysis of sol-gel technology and thin film methods about development of dielectric materials has been given.

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Analysis for Atomic Structural Deterioration and Electrochemical Properties of Li-rich Cathode Materials for Lithium Ion Batteries (리튬이차전지용 리튬과잉계 양극 산화물의 충방전 과정 중 원자 구조 열화 과정과 전기화학 특성에 대한 분석)

  • Park, Seohyeon;Oh, Pilgun
    • Applied Chemistry for Engineering
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    • v.31 no.1
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    • pp.97-102
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    • 2020
  • Recently, various degradation mechanisms of lithium secondary battery cathode materials have been revealed. As a result, many studies on overcoming the limitation of cathode materials and realizing new electrochemical properties by controlling the degradation mechanism have been reported. Li-rich layered oxide is one of the most promising cathode materials due to its high reversible capacity. However, the utilization of Li-rich layered oxide has been restricted, because it undergoes a unique atomic structure change during the cycle, in turn resulting in unwanted electrochemical degradations. To understand an atomic structure deterioration mechanism and suggest a research direction of Li-rich layered oxide, we deeply evaluated the atomic structure of 0.4Li2MnO3_0.6LiNi1/3Co1/3Mn1/3O2 Li-rich layered oxide during electrochemical cycles, by using an atomic-resolution analysis tool. During a charge process, Li-rich materials undergo a cation migration of transition metal ions from transition metal slab to lithium slab due to the structural instability from lithium vacancies. As a result, the partial structural degradation leads to discharge voltage drop, which is the biggest drawback of Li-rich materials.

Influence of the hydrogen post-annealing on the electrical properties of metal/alumina/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

  • Kim, Hee-Dong;An, Ho-Myoung;Seo, Yu-Jeong;Zhang, Yong-Jie;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.122-122
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    • 2008
  • Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

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Capacitance-voltage Characteristics of MOS Capacitors with Ge Nanocrystals Embedded in HfO2 Gate Material

  • Park, Byoung-Jun;Lee, Hye-Ryeong;Cho, Kyoung-Ah;Kim, Sang-Sig
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.8
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    • pp.699-705
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    • 2008
  • Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.