• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.18-23
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• 2009

The effect of hydrogen-nitrogen annealing on the interface trap properties of Metal-Oxide-Nitride-Oxide-Silicon (MONOS) capacitors is investigated by analyzing the capacitors' gate leakage current and the interface trap density between the Si and $SiO_2$ layer. MONOS samples annealed at $850^{\circ}C$ for 30 s by rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing eases $N_2$ and 2% hydrogen and 98% nitrogen gas mixture $(N_2-H_2)$ at $450^{\circ}C$ for 30 mins. Among the three samples as-deposited, annealed in $N_2$ and $N_2-H_2$, MONOS sample annealed in an $N_2-H_2$ environment is found to have the lowest increase of interface-trap density from the capacitance-voltage experiments. The leakage current of sample annealed in $N_2-H_2$ is also lower than that of sample annealed in $N_2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.348-348
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• 2011

Carbon nanotube (CNT) field effect transistors and sensors use CNT as a current channel, of which the resistance varies with the gate voltage or upon molecule adsorption. Since the performance of CNT devices depends very much on the CNT/metal contact resistance, the CNT/electrode contact must be stable and the contact resistance must be small. Depending on the geometry of CNT/electrode contact, it can be categorized into the end-contact, embedded-contact (top-contact), and side-contact (bottom-contact). Because of difficulties in the sample preparation, the end-contact CNT device is seldom practiced. The embedded-contact in which CNT is embedded inside the electrode is desirable due to its rigidness and the low contact resistance. Fabrication of this structure is complicated, however, because each CNT has to be located under a high-resolution microscope and then the electrode is patterned by electron beam lithography. The side-contact is done by depositing CNT electrophoretically or by precipitating on the patterned electrode. Although this contact is fragile and the contact resistance is relatively high, the side-contact by far has been widely practiced because of its simple fabrication process. Here we introduce a simple method to embed CNT inside the electrode while taking advantage of the bottom-contact process. The idea is to utilize a eutectic material as an electrode, which melts at low temperature so that CNT is not damaged while annealing to melt the electrode to embed CNT. The lowering of CNT/Au contact resistance upon annealing at mild temperature has been reported, but the electrode in these studies did not melt and CNT laid on the surface of electrode even after annealing. In our experiment, we used a eutectic Au/Al film that melts at 250$^{\circ}C$. After depositing CNT on the electrode made of an Au/Al thin film, we annealed the sample at 250$^{\circ}C$ in air to induce eutectic melting. As a result, Au-Al alloy grains formed, under which the CNT was embedded to produce a rigid and low resistance contact. The embedded CNT contact was as strong as to tolerate the ultrasonic agitation for 90 s and the current-voltage measurement indicated that the contact resistance was lowered by a factor of 4. By performing standard fabrication process on this CNT-deposited substrate to add another pair of electrodes bridged by CNT in perpendicular direction, we could fabricate a CNT cross junction. Finally, we could conclude that the eutectic alloy electrode is valid for CNT sensors by examine the detection of Au ion which is spontaneously reduced to CNT surface. The device sustatined strong washing process and maintained its detection ability.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.156-156
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• 2000

Recently, the surface electronic states have attracted much attention since their standing wave patterns created around steps, defects, and adsorbates on noble metal surfaces such as Au(111), Ag(110), and Cu(111) were observed by scanning tunneling microscopy (STM). As a typical example, a striking circular pattern of "Quantum corral" observed by Crommie, Lutz, and Eigler, covers a number of text books of quantum mechanics, demonstrating a wavy nature of electrons. After the discoveries, similar standing waves patterns have been observed on other metal and demiconductor surfaces and even on a side polane of nano-tubes. With an expectation that the surface states could be utilized as one of ideal cases for studying two dimensionakl (sD) electronic system, various properties, such as mean free path / life time of the electronic states, have been characterized based on an analysis of standing wave patterns, . for the 2D electron system, electron density is one of the most importnat parameters which determines the properties on it. One advantage of conventional 2D electron system, such as the ones realized at AlGaAs/GaAs and SiO2/Si interfaces, is their controllability of the electrondensity. It can be changed and controlled by a factor of orders through an application of voltage on the gate electrode. On the other hand, changing the leectron density of the surface-state 2D electron system is not simple. On ewqy to change the electron density of the surface-state 2D electron system is not simple. One way to change the electron density is to deposit other elements on the system. it has been known that Pd(111) surface has unoccupied surface states whose energy level is just above Fermi level. Recently, we found that by depositing Pd on Cu(111) surface, occupied surface states of Cu(111) is lifted up, crossing at Fermi level around 2ML, and approaches to the intrinsic Pd surface states with a increase in thickness. Electron density occupied in the states is thus gradually reduced by Pd deposition. Park et al. also observed a change in Fermi wave number of the surface states of Cu(111) by deposition of Xe layer on it, which suggests another possible way of changing electron density. In this talk, after a brief review of recent progress in a study of standing weaves by STM, I will discuss about how the electron density can be changed and controlled and feasibility of using the surface states for a study of 2D electron system. One of the most important advantage of the surface-state 2D electron system is that one can directly and easily access to the system with a high spatial resolution by STM/AFM.y STM/AFM.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• ETRI Journal
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• v.24 no.4
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• pp.290-298
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• 2002

We present, for the first time, a prototype active-matrix field emission display (AMFED) in which an amorphous silicon thin-film transistor (a-Si TFT) and a molybdenum-tip field emitter array (Mo-tip FEA) were monolithically integrated on a glass substrate for a novel active-matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low-voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a-Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a-Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for $n^+-doped$ a-Si etching with high etch selectivity to intrinsic a-Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a-Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a-Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low-voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.221-221
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• 2013

Striving to replace the well known silicon nanocrystals embedded in oxides with solution-processable charge-trapping materials has been debated because of large scale and cost effective demands. Herein, a silicon quantum dot-polystyrene nanocomposite (SiQD-PS NC) was synthesized by postfunctionalization of hydrogen-terminated silicon quantum dots (H-SiQDs) with styrene using a thermally induced surface-initiated polymerization approach. The NC contains two miscible components: PS and SiQD@PS, which respectively are polystyrene and polystyrene chains-capped SiQDs. Spin-coated films of the nanocomposite on various substrate were thermally annealed at different temperatures and subsequently used to construct metal-insulator-semiconductor (MIS) devices and thin film field effect transistors (TFTs) having a structure p-$S^{++}$/$SiO_2$/NC/pentacene/Au source-drain. C-V curves obtained from the MIS devices exhibit a well-defined counterclockwise hysteresis with negative fat band shifts, which was stable over a wide range of curing temperature ($50{\sim}250^{\circ}C$. The positive charge trapping capability of the NC originates from the spherical potential well structure of the SiQD@PS component while the strong chemical bonding between SiQDs and polystyrene chains accounts for the thermal stability of the charge trapping property. The transfer curve of the transistor was controllably shifted to the negative direction by chaining applied gate voltage. Thereby, this newly synthesized and solution processable SiQD-PS nanocomposite is applicable as charge trapping materials for TFT based memory devices.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.