• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.318-321
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• 2000

We showed that the change of Ar to $N_2$flow during the TiN deposition by the reactive sputtering decides the crystallinity of LPCVD W, as well as the electrical properties of the W-TiN/SiO$_2$Si capacitor. In particular, the threshold voltage can be controlled by the Ar to $N_2$ratio. As compared to the results obtained from the LPCVD W/SiO$_2$/Si MOS capacitor, the insertion of approximately 50 nm TiN film effectively prohibits the fluorine diffusion during the deposition and annealing of W films, resulting in negligible leakage currents at the low electric fields.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.91-96
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• 1992

The technology of LOCOS(LOCal Oxidation of Silicon) was used to form the island of SOI film. After this, the SOI film was recrystallized by CO$_2$ laser and metal gate nMOSFETs were fabricated on this SOI film and their electrical characteristics were measured. The kink effect was not nearly observed and edge channel effect was found in the SOI nMOSFETs. The threshold voltage was about 0.5V, the electron mobility was about 340cm$^2$V$\cdot$S and an ON/OFF ratio above 10$^{5}$ was obtained at V_{DS}$=4V. The electrical characteristics were improved by laser recrystallization.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.101.1-101.1
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• 2016

Van der Waals (vdW) heterostructures built from two-dimensional layered materials provide an unprecedented opportunity in designing new material systems because the lack of dangling bonds on the vdW surfaces enables the creation of high-quality heterointerfaces without the constraint of atomically precise commensurability. In particular, the ability to build artificial heterostructures, combined with the recent advent of transition metal dichalcogenides, allows the fabrication of unique semiconductor heterostructures in an ultimate thickness limit for fundamental studies as well as novel device applications. In this talk, we will present the characterization of the electronic and optoelectronic properties of atomically thin p-n junctions consisting of vertically stacked WSe2 and MoS2 monolayers. We observed gate-tunable diode-like current rectification and a photovoltaic response across the p-n interface. Unlike conventional bulk p-n junctions, the tunneling-assisted interlayer recombination of the majority carriers is responsible for the tenability of the charge transport and the photovoltaic response. Furthermore, we will discuss the enhanced optoelectronic characteristics in graphene-sandwiched vdW p-n junctions.

• Transactions of Materials Processing
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• v.5 no.3
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• pp.239-255
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• 1996

A new forming technology has been developed to fabricate near-net shape products using light metal. A semi-solid forming technology has some advantages compared with the conventional forming processes such as die casting squeeze casting and hot/cold forging. In this study the numerical analysis of semi-solid filling for a straight die shape and orifice die shape in gate pattern is studied on semi-solid materials(SSM) of solid fraction fs =30% in A356 aluminum alloy. The finite difference program of Navier-Stokes equation coupled with heat transfer and solidification has been developed to predict a filling pattern and the temperature distribution of SSM. The programdeveloped in this study gives die filling patterns of SSM and final solidifica-tion region.

• ETRI Journal
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• v.30 no.2
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• pp.308-314
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• 2008

In this paper, we describe the fabrication of 3.5-inch QCIF active matrix organic light emitting display (AMOLED) panels driven by thin film transistors, which are produced by an ultra-low-temperature polycrystalline silicon process on plastic substrates. The over all processing scheme and technical details are discussed from the viewpoint of mechanical stability and display performance. New ideas, such as a new triple-layered metal gate structure to lower leakage current and organic layers for electrical passivation and stress reduction are highlighted. The operation of a 3.5-inch QCIF AMOLED is also demonstrated.

• Journal of the Korean Vacuum Society
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• v.4 no.1
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• pp.18-25
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• 1995

건식, 습식, 건식/습식 산화분위기로 성장한 게이트 산화막 위에 AI, 인 도핑된 다결정시리콘, 비정질 실리콘/인 도핑된 다결정 실리콘을 증착하여 제작한 금속-산화물-반도체(metal-oxide-semiconductor:MOS)의 전기적 특성을 순간 절연파괴(TZDB), 정전용량-전압(C-V)과 경시절연파괴(TDDB)로 평가하였다. AI 게이트에서 습식산화막과 건식산화막의 평균 파괴전계는 각각 9.0MV/cm, 7.7MV/cm이였고, 습식산화막의 평균 파괴전계가 8.4MV/cm 이였으며, AI 게이트보다 0.6MV/cm 정도 낮았다. 이것은 다결정 실리콘/습식산화막 계면에서 인(phosphorus) 확산으로 다결정 실리콘의 grain 성장과 산화막의 migration에 의한 roughness 증가에 기인한다. 그러나 다결정 실리콘/건식산화막 계면에서 roughness 증가는 없었다. 다결정 실리콘 게이트에서는 건식/습식 산화막이 건식산화막과 습식산화막보다 평균 파괴전계와 절연파괴전하(QBD)가 높았다. 또한 다결정/비정질 실리콘 게이트에서는 습식산화막의 평균 파괴전계가 8.8MV/cm이였으며, 다결정 실리콘 게이트에서보다 0.4MV/cm 정도 높았다. 다결정/비정질 실리콘 구조는 앞으로 VLSI 적용에 있어서 게이트 전극으로 매우 유용할 것이다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.123-123
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• 2003

나노튜브는 반도체 재료로서 뿐만 아니라 다른 분야로까지 다양한 응용범위를 가진 물질로서 기존에는 주의 탄소를 사용하여 제작, 사용되어지고 있으나 게이트옥사이드(Gate Oxide) 물질인 지르코니아(ZrO$_2$), 타이타니아(TiO2$_2$) 등을 이용한 나노튜브는 많이 제작되어지고 있지 못하다. 따라서 보다 나은 성질을 갖는 물질로서 나노튜브를 제작할 시 반도체 재료에서의 고집적화를 통해 좋은 성질을 갖게 할 수 있으며 여러 분야로까지 확대가 가능한 재료를 사용하여 광학 및 환경분야 등 응용범위를 넓힐 수 있다. 본 실험은 나노튜브 제작에 있어서 템플레이트의 구멍 내부를 ALD 기술을 이용하여 균일한 두께를 갖는 금속 산화물층을 성장시킨 후 템플레이트 재료의 식각을 통해 금속산화물 나노튜브가 남아있게 하여 제작하는 방법이다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• Transactions on Electrical and Electronic Materials
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• v.4 no.4
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• pp.26-29
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• 2003

To discover electrical properties of individual single wall nanotube(SWNT), a number of SWNT-based tubeFETs have been fabricated. The device consists of a single semiconducting SWNT on an insulating substrate, contacted at each end by metal electrodes. It presents high transconductances, and charge storage phenomenon, which is the operations of injecting electrons from the nanotube channel of a tubeFET into charge traps on the surface of the $SiO_2$ gate dielectric, thus shifting the threshold voltage. This phenomenon can be repeated many times, and maintained for the hundreds of seconds at room temperature. We will report this phenomenon as the memory effects of the SWNT, and attempt to use this property for the memory device.