• 제목/요약/키워드: Memory testing

검색결과 243건 처리시간 0.025초

Cherry Tomatoes Ameliorate Scopolamine-induced Amnesia in Mice

  • Choi, Won-Hee;Ahn, Ji-Yun;Kim, Su-Na;Ha, Tae-Youl
    • Preventive Nutrition and Food Science
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    • 제13권4호
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    • pp.281-285
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    • 2008
  • Cherry tomatoes are rich in antioxidants, which may protect against neurodegeneration and consequent memory loss. This study was conducted to investigate the effect of cherry tomatoes on scopolamine-induced amnesia in mice. Male ICR mice (4 weeks old) were maintained for 4 weeks on a diet containing 10 or 20% tomato powder (TP), and then administered scopolamine (1 mg/kg body weight, i.p.) 45 min before memory testing. Passive avoidance and Morris water maze testing revealed that scopolamine-induced amnesia was significantly reduced in the TP groups compared to the non TP-received (control) group. Accordingly, acetylcholinesterase activities in the serum and brain of TP groups were lower than those in the control group. These findings suggest that cherry tomatoes may be useful for the prevention of neurodegenerative diseases such as amnesia and Alzheimer's disease.

RAM의 최소 테스트 패턴에 관한 연구 (A Study on the Minimal Test Pattern of the RAM)

  • 김철운;정우성;김태성
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1996년도 추계학술대회 논문집
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    • pp.23-25
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    • 1996
  • In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

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A Very Efficient Redundancy Analysis Method Using Fault Grouping

  • Cho, Hyungjun;Kang, Wooheon;Kang, Sungho
    • ETRI Journal
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    • 제35권3호
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    • pp.439-447
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    • 2013
  • To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.

An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories

  • Kang, Dong-Chual;Park, Sung-Min;Cho, Sang-Bock
    • ETRI Journal
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    • 제26권6호
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    • pp.520-534
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    • 2004
  • As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

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Nootropic Potential of Murraya koenigii leaves in Rats

  • Vasudevan, Mani;Parle, Milind;Sengottuvelu, Singaravel;Shanmugapriya, Thulasimani
    • Advances in Traditional Medicine
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    • 제8권4호
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    • pp.365-373
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    • 2008
  • Murraya koenigii leaves commonly known as 'curry patta' are routinely added to Indian gravy and vegetarian dishes by south Indian as a favourate condiment. The present study was undertaken to investigate the effects of Murraya koenigii leaves (MKL) on memory in rats. Elevated plus-maze and Hebb-Williams maze served as the exteroceptive behavioral models for testing memory. Diazepam-, scopolamine- and ageing-induced amnesia served as the interoceptive behavioral models. MKL fed orally to various groups of young and aged rats with diet containing 2, 4 and 8% w/w of MKL for 30 days consecutively were investigated. The MKL diets produced a significant dose-dependent improvement in memory scores of young and aged rats and significantly reduced the amnesia induced by scopolamine (0.4 mg/kg, i.p.) and diazepam (1 mg/kg, i.p.). Therefore, it would be worthwhile to specifically investigate the therapeutic potential of MKL in the management of dementia patients.

Ti-42.5at.%Ni-10at.%Cu합금의 형상기억특성에 관한 연구 (A Study on the Shape Memory Characteristic Behaviors of Ti-42.5at%Ni-10at.% Cu Alloys)

  • 우흥식;박용규
    • 한국안전학회지
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    • 제24권1호
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    • pp.26-30
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    • 2009
  • Shape memory recoverable stress and strain of Ti-42.5at%Ni-10at%Cu alloys were measured by means of constant temperature tensile tests. The alloys' transformation behavior is B2 - B19 by DSC result. The strain by tensile stress were perfectly recovered by heating at any testing conditions but shape memory recoverable stress increased to 66MPa and then slightly decreased. Transformation temperatures from thermal cycling under constant uniaxial applied tensile loads linearly increased by increasing tensile load and their thermal hysteresis are about 110K and their maximum recoverable strain is 6.5% at 100MPa condition.

A Distributed Control Architecture for Advanced Testing In Realtime

  • Thoen Bradford K.;Laplace Patrick N.
    • 한국지진공학회:학술대회논문집
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    • 한국지진공학회 2006년도 학술발표회 논문집
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    • pp.563-570
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    • 2006
  • Distributed control architecture is based on sharing control and data between multiple nodes on a network Communication and task sharing can be distributed between multiple control computers. Although many communication protocols exist, such as TCP/IP and UDP, they do not have the determinism that realtime control demands. Fiber-optic reflective shared memory creates the opportunity for realtime distributed control. This architecture allows control and computational tasks to be divided between multiple systems and operate in a deterministic realtime environment. One such shared memory architecture is based on Curtiss-Wright ScramNET family of fiber-optic reflective memory. MTS has built seismic and structural control software and hardware capable of utilizing ScramNET shared memory, opening up infinite possibilities in research and new capabilities in Hybrid and Model-In-The-Loop control.

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A Study of Resource Utilization Improvement on Cloud Testing Platform

  • Kuo, Jong-Yih;Lin, Hui-Chi;Liu, Chien-Hung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제15권7호
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    • pp.2434-2454
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    • 2021
  • This paper developed the software testing factory-cloud testing platform (STF-CTP) to address the software compatible issues in various smart devices. Software developers who only require uploading the application under test (AUT) and test script can test plenty of smart devices in STF-CTP. The challenge for the cloud test platform is how to optimize the resource and increase the performance in the limited resource. This paper proposed a new scheduling mechanism and a new process of the system operation which is based on the OpenStack platform. We decrease about 40% memory usage of OpenStack server, increase 3% to 10% Android device usage of STF-CTP, enhance about 80% test job throughput and reduces about 40% test job average waiting time.

Ti-42.5at.%Ni-2.0at.%Cu합금의 인장 및 압축에 따른 형상기억특성에 관한 연구 (A Study on the Shape Memory Characteristic Behaviors of Ti-42.5at.%Ni-2.0at.%Cu Alloys in Tension and Compression Condition)

  • 우흥식;조재환;박용규
    • 한국안전학회지
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    • 제24권5호
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    • pp.1-5
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    • 2009
  • NiTiCu alloys can produce a large force per unit volume and operate with a simple mechanism. For this reasons, it has been widely studied for application as a micro actuator. So in this study, one-way and two way shape memory effects of Ti-42.5at%Ni-2.0at%Cu alloys are studied. In the case of one-way shape memory effects, shape memory recoverable stress and strain of this alloys were measured by means of tension and compression tests under constant temperature. The strains by tension and compression stress were perfectly recovered by heating at any testing conditions also shape memory recoverable stress increased to 116 MPa in tension tests and to 260 MPa in compression tests. In the case of two-way shape memory effects, transformation temperatures from thermal cycling under constant uniaxial applied tension and compression loads linearly increased by increasing external loads and their maximum recoverable strain is 3.8% at 100MPa tensile condition and 2.2% at 125 MPa compression condition.

Hamming distance를 고려한 경로 지연 고장의 built-in self-testing 기법 (Built-in self-testing techniques for path delay faults considering hamming distance)

  • 허용민
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 하계종합학술대회논문집
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    • pp.807-810
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    • 1998
  • This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

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