ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

A Very Efficient Redundancy Analysis Method Using Fault Grouping

  • Cho, Hyungjun (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Wooheon (Department of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical & Electronic Engineering, Yonsei University)
  • Received : 2012.07.17
  • Accepted : 2012.11.06
  • Published : 2013.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree-based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.

Keywords

References

  1. Y. Zorian, "Embedded Memory Test & Repair: Infrastructure IP for SoC Yield," Proc. IEEE Int. Test Conf. (ITC), Baltimore, MD, USA, Oct. 2002, pp. 340-349.
  2. J.R. Day, "A Fault-Driven, Comprehensive Redundancy Algorithm," IEEE Design Test, vol. 2, no. 3, June 1985, pp. 35-44.
  3. S.-Y. Kuo and W.K. Fuchs, "Efficient Spare Allocation in Reconfigurable Arrays," Proc. 23rd ACM/IEEE Design Autom. Conf. (DAC), Las Vegas, NV, USA, June 1986, pp. 385-390.
  4. C.-L. Wey and F. Lombardi, "On the Repair of Redundant RAM's," IEEE Trans. Computer-Aided Design, vol. 6, no. 2, Mar. 1987, pp. 222-231. https://doi.org/10.1109/TCAD.1987.1270266
  5. R.W. Haddad, A.T. Dahbura, and A.B. Sharama, "Increased Throughput for the Testing and Repair of RAM's with Redundancy," IEEE Trans. Computers, vol. 40, no. 2, Feb. 1991, pp. 154-166. https://doi.org/10.1109/12.73586
  6. V.G. Hemmady and S.M. Reddy, "On the Repair of Redundant RAMs," Proc. Design Autom. Conf., June 1989, pp. 710-713.
  7. H. Cho, W. Kang, and S. Kang, "A Fast Redundancy Analysis Algorithm in ATE for Repairing Faulty Memories," ETRI J., vol. 34, no. 3, June 2012, pp. 478-481.
  8. P. Öhler, S. Hellebrand, and H.-J. Wunderlich, "An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy," Proc. European Test Symp. (ETS), May 2007, pp. 91-96.
  9. W. Jeong et al., "An Advanced BIRA for Memories with an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 29, no. 12, Dec. 2010, pp. 2014-2026. https://doi.org/10.1109/TCAD.2010.2062830
  10. T. Kawagoe et al., "A Built-in Self Repair Analyzer (CRESTA) for Embedded DRAMs," Proc. IEEE Int. Test Conf. (ITC), Oct. 2000, pp. 567-574.
  11. H. Cho, W. Kang, and S. Kang, "A Built-In Redundancy Analysis with a Minimized Binary Search Tree," ETRI J., vol. 32, no. 4, Aug. 2010, pp. 638-641. https://doi.org/10.4218/etrij.10.0210.0032
  12. M. Tarr, D. Boudreau, and R. Murphy, "Defect Analysis System Speeds Test and Repair of Redundant Memories," Electronics, Jan. 1984, pp. 175-179.
  13. C.-T. Huang et al., "Built-In Redundancy Analysis for Memory Yield Improvement," IEEE Trans. Reliability, vol. 52, no. 4, Dec. 2003, pp. 386-399. https://doi.org/10.1109/TR.2003.821925
  14. W. Jeong et al., "A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 17, no. 12, Dec. 2009, pp. 1665-1678. https://doi.org/10.1109/TVLSI.2008.2005988
  15. T.-J. Chen, J.-F. Li, and T.-W. Tseng, "Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 31, no. 6, June 2012, pp. 930-940. https://doi.org/10.1109/TCAD.2011.2181510
  16. M.B. Healy and et al., "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory," Proc. IEEE Custom Integrated Circuits Conf. (CICC), San Jose, CA, USA, Sept. 2010, pp. 1-4.
  17. H. Saito et al., "A Chip-Stacked Memory for On-Chip SRAMRich SoCs and Processors," IEEE J. Solid-State Circuits, vol. 45, no. 1, Jan. 2010, pp. 15-22. https://doi.org/10.1109/JSSC.2009.2034078
  18. C.-W. Wu, S.-K. Lu, and J.-F. Li, "On Test and Repair of 3D Random Access Memory," Proc. Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 744-749.
  19. J. Lee, K. Park, and S. Kang, "Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers," ETRI J., vol. 34, no. 3, June 2012, pp. 388-398. https://doi.org/10.4218/etrij.12.0111.0643
  20. H.-Y. Lin, F.-M. Yeh, and S.Y. Kuo, "An Efficient Algorithm for Spare Allocation Problems," IEEE Trans. Reliability, vol. 55, no. 2, June 2006, pp. 369-378. https://doi.org/10.1109/TR.2006.874942

Cited by

  1. Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis vol.37, pp.7, 2013, https://doi.org/10.1109/tcad.2017.2760505
  2. Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair vol.24, pp.5, 2013, https://doi.org/10.1145/3339851