• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.57-62
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• 2022

Recently, fast storage media such as phage-change memory (PCM) emerge, and memory management policies for slow disk storage need to be revisited. In this paper, we propose a new page replacement policy that makes use of PCM as a swap device of virtual memory systems. The proposed policy aims at reducing write traffic to the swap device as well as reducing the number of page faults pursued by traditional page replacement policies. This is because a write operation in PCM is slow and PCM has limited write endurances. Specifically, the proposed policy focuses on the reduction of page faults when the memory load of the system is high, but it aims at reducing write traffic to storage when free memory space is sufficient. Simulation experiments with various memory reference traces show that the proposed policy reduces write traffic to PCM without performance degradations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.166-174
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• 2010

SSDs are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional index management schemes based on B-Tree due to the relatively slow characteristics of flash memory operations, as compared to RAM memory. In order to achieve this goal, we propose a new index management scheme based on a compressed hot-cold clustering called CHC-Tree. CHC-Tree-based index management improves index operation performance by dividing index nodes into hot or cold segments and compressing pointers and keys in the index nodes and clustering the hot or cold segments. The offset compression techniques using unused free area in cold index node lead to reduce the number of slow erase operations in index node insert/delete processes. Simulation results show that our scheme significantly reduces the write and erase operation overheads, improving the index search performance of B-Tree by up to 26 percent, and the index update performance by up to 23 percent.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.441-450
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• 2002

As the size of embedded system software increase bigger and bigger, and it's complexity is grower and grower, the usage of dynamic memory management scheme such collector also has been increased. Using the garbage collector, however, inherently lead us performance degradation. In order to resolve this kind of performance problem in the Java based embedded system. we introduce an explicit dynamic memory free method to the automated dynamic memory management environment. which can be performed by a programmer. In the worst case, the prosed scheme shows the same performance as the case of that only garbage collector is working, since the unclaimed garbage objects will eventually be collected later by the garbage collector. In the best case. our method is free from any runtime overhead because the applications can be implemented without any intervention of the garbage collector. Although the proposed method can be facilitated with all the existing garbage collection algorithms, it shows an outperform in the case of mark-and-sweep algorithm.

• KIPS Transactions on Software and Data Engineering
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• v.10 no.5
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• pp.187-194
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• 2021

A person's behavioral recognition is the recognition of what a person does according to joint movements. To this end, we utilize computer vision tasks that are utilized in image processing. Human behavior recognition is a safety accident response service that combines deep learning and CCTV, and can be applied within the safety management site. Existing studies are relatively lacking in behavioral recognition studies through human joint keypoint extraction by utilizing deep learning. There were also problems that were difficult to manage workers continuously and systematically at safety management sites. In this paper, to address these problems, we propose a method to recognize risk behavior using only joint keypoints and joint motion information. AlphaPose, one of the pose estimation methods, was used to extract joint keypoints in the body part. The extracted joint keypoints were sequentially entered into the Long Short-Term Memory (LSTM) model to be learned with continuous data. After checking the behavioral recognition accuracy, it was confirmed that the accuracy of the "Lying Down" behavioral recognition results was high.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.1-6
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• 2022

With the emergence of the new era of the 4th industrial revolution, compute-bound workloads with large memory footprint like big data processing increase dramatically. Even in such compute-bound workloads, however, we observe bulky I/Os while loading big data from storage to memory. Although file I/O cache plays a role of accelerating the performance of storage I/O, we found out that the cache hit rate in such environments is not improved even though we increase the file I/O cache capacity because of some special I/O references generated by compute-bound workloads. To cope with this situation, we propose a new file I/O cache management policy that improves the cache hit rate for compute-bound workloads significantly. Trace-driven simulations by replaying file I/O reference logs of compute-bound workloads show that the proposed cache management policy improves the cache hit rate compared to the well-acknowledged CLOCK algorithm by a large margin.

• Journal of KIISE:Information Networking
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• v.32 no.4
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• pp.443-451
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• 2005

Stateful inspection devices must maintain flow information. These devices create the flow information also for network attack packets, and it can fatally inflate the dynamic memory allocation on stateful inspection devices under network attacks. The memory inflation leads to memory overflow and subsequent performance degradation. In this paper, we present a guideline to set the flow entry timeout for a stateful inspection device to remove harmful embryonic entries created by network attacks. Considering Transmission Control Protocol (TCP) if utilized by most of these attacks as well as legitimate traffic, we propose a parsimonious memory management guideline based on the design of the TCP and the analysis of real-life Internet traces. In particular, we demonstrate that for all practical purposes one should not reserve memory for an embryonic TCP connection with more than (R+T) seconds of inactivity where R=0, 3, 9 and $1\leqq{T}\leqq{2}$ depending on the load level.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.6
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• pp.567-582
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• 2000

We propose a new way of managing flash memory space for flash memory-specific file system based on log-structured file system. Flash memory has attractive features such as non-volatility, and fast I/O speed, but it also suffers from inability to update in place and limited usage cycles. These drawbacks require many changes to conventional storage (file) management techniques. Our focus is on lowering cleaning cost and evenly utilizing flash memory cells while maintaining a balance between the two often-conflicting goals. The proposed cleaning method performs well especially when storage utilization and the degree of locality are high. The cleaning efficiency is enhanced by dynamically separating cold data and non-cold data. The second goal, cycle-leveling is achieved to the degree where the maximum difference between erase cycles is below the error range of the hardware. Simulation results show that the proposed method has significant benefit over naxve methods: maximum of 35% reduction in cleaning cost with even spreading writes across segments.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.285-291
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• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.