• Journal of the Semiconductor & Display Technology
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• v.7 no.3
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• pp.17-21
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• 2008

Application of flash memory in mobile and ubiquitous related devices is rapidly being increased due to its low price and high performance. In addition, some notebook computers currently come out into market with a SSD(Solid State Disk) instead of hard-drive based storage system. Regarding this trend, applications need to increase the storage capacity using multiple flash memory chips for larger capacity sooner or later. Flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its physical property. In order to make flash memory storage work with tangible performance, reclaiming of invalid regions needs to be controlled in a particular manner to decrease the number of erasures and to distribute the erasures uniformly over the whole memory space as much as possible. In this paper, we study the performance of flash memory recycling algorithms and demonstrate that the proposed algorithm shows acceptable performance for flash memory storage with multiple chips. The proposed cleaning method partitions the memory space into candidate memory regions, to be reclaimed as free, by utilizing threshold values. The proposed algorithm handles the storage system in multi-layered style. The impact of the proposed policies is evaluated through a number of experiments.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.10 s.181
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• pp.2461-2468
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• 2000

In this paper, single fiber pull-out test is used to measure the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory alloy composite with temperature. Fiber and matrix of $Ti_{50}-Ni_{50}$ shape memory alloy composite are respectively $Ti_{50}-Ni_{50}$ shape memory alloy and epoxy resin. To strengthen the interfacial bonding shear stress, various surface treatments are used. They are the hand-sanded surface treatment, the acid etched surface treatment and the silane coupled surface treatment etc.. The interfacial bonding shear strength of surface treated shape memory alloy fiber is greater than that of surface untreated shape memory alloy fiber by from 10% to 16%. It is assured that the hand-sanded surface treatment and the acid etched surface treatment are the best way to strengthen the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory composite. The best treatment condition of surface is 10% HNO$_3$ solution in the etching method to strengthen the interfacial bonding shear strength of $Ti_{50}-Ni_{50}$ shape memory alloy composite.

• Journal of International Academy of Physical Therapy Research
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• v.9 no.4
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• pp.1591-1595
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• 2018

The number of healthy older adults is rapidly increasing recently owing to the increase of the elderly population. Therefore, programs for improving the cognitive functions of these healthy seniors are actively being expanded. This study aimed to prevent the decline of cognitive function due to aging by applying a program enhancing cognitive functions to healthy older adults. The objective of this study was to evaluate the effects of Korean computer-based cognitive rehabilitation program (CoTras), which is commonly used in cognitive therapy for the aging, on the memory of the elderly. The subjects had scored at least 24 points in MMSE-K. CoTras was applied once a week (30 minutes) for one month. Electronic pegboard programs were used as an evaluation tool: order memory (difficulty=low) and location memory (difficulty=medium). The order and location memories were compared before and after the intervention. The Wilcoxon signed rank-sum test was used for the study at the significance level of ${\alpha}=.05$. The results showed that CoTras significantly improved order memory and location memory. Therefore, CoTras can be applied to the healthy elderly for improving that memory improvement training has a positive impact on healthy older adults result in the development of memory enhancement programs can be expanded in the future.

• International journal of advanced smart convergence
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• v.10 no.2
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• pp.73-78
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• 2021

Recently, the number of people who visit the hospital due to diabetes is increasing. According to the Korean Diabetes Association, it is statistically indicated that one in seven adults aged 30 years or older in Korea suffers from diabetes, and it is expected to be more if the pre-diabetes, fasting blood sugar disorders, are combined. In the last study, the validity of Triglyceride and Cholesterol associated with diabetes was confirmed and analyzed using Random Forest. Random Forest has a disadvantage that as the amount of data increases, it uses more memory and slows down the speed. Therefore, in this paper, we compared and analyzed Random Forest and XGBoost, focusing on improvement of learning speed and prevention of memory waste, which are mainly dealt with in machine learning. Using XGBoost, the problem of slowing down and wasting memory was solved, and the accuracy of the diabetes recognition factor was further increased.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.485-488
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• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• Journal of Information Display
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• v.9 no.1
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• pp.6-13
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• 2008

Mobile phones use the embedded memory in LDI (LCD Driver IC). In memory accessing mode, data overlapping phenomenon can occur. These days, various contents such as DMB, Camera, Game are merged to phone. Accordingly, with more data transmission, there would be more data overlapping phenomenon in memory accessing mode. Human eyes perceive this data overlapping phenomenon as simply horizontal line noise. The cause of the data overlapping phenomenon was analysed in this paper. The data overlapping phenomenon can be changed by the speed of data transmission between the host and LDI. The optimum memory accessing position can be defined. This paper proposes a new algorithm for avoiding data overlapping.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.