• 융합신호처리학회논문지
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• 제2권4호
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• pp.46-52
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• 2001

방사광을 이용한 형강 X선 CT 이미징의 고속화를 위한 촬상 시스템과 처리 알고리즘을 검토하였다. 본 논문에서 사용된 촬상시스템은 고계수율 영역에서 안정된 동작을 한 전자 시스템으로 불감시간이 약 6%로 감소되고 계측시간의 경우도 1 점 당 3초로 단축되었다. 또한 재구성 알고리즘의 효율화를 증명하였고, 메모리와 계산량을 약 1/100로 감소시켰다. 물리적 phantom으로 그 정량성을 확인하였고, 시험관내의 갑상선의 화상으로부터 요드 분포를 추정하였다. 이러한 결과는 생체내에서 형광 X선 CT 계측의 실현 가능성을 보여준 것이다.

• 한국컴퓨터정보학회논문지
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• 제16권8호
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• pp.19-27
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• 2011

과거 접근제어에 대한 연구는 효율적인 측면보다 안전성에 더 많은 초점이 맞추어져 있었다. 본 연구는 배터리나 메모리 등의 자원이 제약적인 개인 휴대용 단말기와 같은 환경에서 XML 데이터 스트림의 효율적이고 안전한 질의처리에 대한 방법을 제안한다. 특히, 본 연구는 접근제어 처리과정에서 발생할 수 있는 추가적인 오버헤드를 각 질의처리 단계별로 찾아내고 최소화하여, 자원의 사용을 최적화하며 안전한 결과를 얻기 위한 최소한의 오버헤드를 갖는 접근제어 처리 방법을 제안한다. 끝으로, 실험을 통해 본 연구에서의 제안방법에 대한 우수성 분석을 하였다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.351-352
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• 2007

The sensor networking technique as the radio network which does not have the base infrastructure network. The sensor nodes oneself automatic compose the network and simultaneously accomplish two roles of the router and data source. The sensor network is kind of Ad-hoc network is a possibility of seeing from point. sensor networking technique is restricted that limit of the memory and the battery back with the resources of the node. The sensor nodes overcomes the restriction of the resources it is in the process of researching the multi-hop routing technique which the sensor network divided cluster routing techniques which are researched. this paper proposed using beamforming antenna which has the directivity of the electric wave. the beamforming antenna from the Ad-hoc network using technique. the proposal is that raises the efficient of data trans mission from the sensor network and extends the lift time of the sensor network.

• Journal of Information Technology Applications and Management
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• 제26권4호
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• pp.1-18
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• 2019

The virtual reality (VR) is an immerging technology used in the serious games industry to treat psychological disorders like dementia. We created a system named as Virtual Reality Home (VRH) for the elderly who lived with Alzheimer's disease (or other form of dementia) and cognitive impairment using virtual reality technology. The purpose of our study is to measure the long-time immersion and retention of VRH on the moods and apathy, enhancement in physical and brain stimulation as well as a decision making with peoples of dementia and explore the experience of aged care home staff's member. The VRH shows a positive impact on the elderly participants and staff members. During the VRH experience, excitement and a great level of alertness were observed among the participants but few of them were feeling anxiety. Furthermore, we observed the improvement in physical, memory and brain stimulation, but the participants have a low focus on decision making because they wanted to explore all interactable objects in the VRH. This study suggests that the VR may have the potential to improve the quality of life, and these results can assist to expand the future development in the enhancement of efficiency of people with dementia.

• Structural Engineering and Mechanics
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• 제45권6호
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• pp.759-777
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• 2013

In this paper, a topology optimization method based on the element independent nodal density (EIND) is developed for continuum solids with multiple load cases and multiple constraints. The optimization problem is formulated ad minimizing the volume subject to displacement constraints. Nodal densities of the finite element mesh are used a the design variable. The nodal densities are interpolated into any point in the design domain by the Shepard interpolation scheme and the Heaviside function. Without using additional constraints (such ad the filtering technique), mesh-independent, checkerboard-free, distinct optimal topology can be obtained. Adopting the rational approximation for material properties (RAMP), the topology optimization procedure is implemented using a solid isotropic material with penalization (SIMP) method and a dual programming optimization algorithm. The computational efficiency is greatly improved by multithread parallel computing with OpenMP to run parallel programs for the shared-memory model of parallel computation. Finally, several examples are presented to demonstrate the effectiveness of the developed techniques.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2014년도 제49차 동계학술대회논문집 22권1호
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• ETRI Journal
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• 제33권5호
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• 제어로봇시스템학회논문지
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• 제4권2호
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• pp.194-202
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• 1998

This paper describes a hardware implementation method of a Petri Net-based controller. A flexible and systematic implementation method, based on look-up tables, is suggested, which enables to build high speed Petri net-based controllers. The suggested method overcomes the inherent speed limit that arises from the microprocessors by using of matrix-based look-up tables. Based on the matrix framework, this paper suggests various specific data path structures as well as a basic data path structure, accompanied by evolution algorithms, for sub-class Petri nets. A new sub-class Petri net, named Biarced Petri Net, resolves memory explosion problem that usually comes with matrix-based look-up tables. The suggested matrix-based method based on the Biarced Petri net has as good efficiency and expendability as the list-based methods. This paper shows the usefulness of the suggested method, evaluating the size of the look-up tables and introducing an architecture of the signal processing unit of a programmable controller. The suggested implementation method is supported by an automatic design support program.

• 대한전자공학회논문지
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• 제17권5호
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• pp.36-42
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• 1980

본 연구에서는, 8085CPU 4대를 사용하여서, 주마이크로프로세서의 버스에 DMA장치를 통하여 종마이크로프로세서에 접속되는 복합마이크로프로세서 시스템을 설계하여서 병렬처리 시킴으로서 처리효율을 높일 수 있었다. 마이크로프로세서의 동작대수와 시스템 Throughput의 관계를 측정한 결과, 이상치의 70∼80퍼센트 정도에 머무는 결과를 얻었다. 자원의 할당이나 일정계획은 주마이크로프로세서가 이루도록 하였고, 마이크로프로세서 사이의 통신 및 공유데이터의 격납은 공유메모리를 사용하도록 하였다. 또한 직렬로 작성된 원시프로그램으로 부터 병렬성을 검출하는 방법을 제시하였다.