• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

• The Magazine of the IEIE
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• v.39 no.9
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• pp.39-46
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• 2012

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5465-5470
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• 2012

FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.32-37
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• 1982

This paper shows a design method of English/Hanguel/Chinese display controller using address conversion thchnique and DMA in the raster scanning graphic CRT display by giving a design example (64 characters$\times$16 lines display controller).

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.584-588
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• 1991

This paper presents a fuzzy adaptive controller which can improve the control policy automatically. Adaptation is achieved by the addition of on-line identification of the fuzzy inverse model using input-output data pairs of the process. Starting with an initial crude control rule, the adaptive controller matches the model to the process to self-tune the controller. The control algorithm needs much less memory of computer than other SOC algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.5
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• pp.539-548
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• 2015

In this paper, shared memory feature was developed in multi-core system with different OS for different processor-specific bus, while conducting an experiment on shared memory feature between the two processors based on embedded Linux system. For the purpose of developing shared memory in dual bus structure, memory controller was used, while managing shared memory segment through list data structure. For AMP multi-core test, Linux OS was installed in 2 processor cores. In addition, it verified the creation and use of shared memory by using kernel module implemented to test shared memory.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.342-347
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• 1993

For a fast evolution, a memory-based implementation of a petri net is discussed. A sub-class petri net model called B-petri net is suggested to make a memory-based implementation feasible in a large size application. The suggested B-petri net is a binary-petri net since only a binary-typed decision, fork and join are allowed. The application of a B-petri nt is focused to a SFC(sequential function chart) program. The memory requirement, speed and computational load are compared with a petri net when they are implementated by a memory-based method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.8
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• pp.344-351
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• 2002

The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response. We use the proposed algorithm to solve parameter optimization problems. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore the usefulness of memory-cell mechanism in immune algorithm is without. This paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verified performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. The results of Computer simulations represent that the proposed immune algorithm shows a fast convergence speed and a good control performances under the varying system parameters.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.10
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• pp.67-76
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• 2008

In this research, a simple technique for designing PID controller, which guarantees robust stability for two-mass systems with parameter uncertainties as well as rigid-body behavior and zero steady-state error,is described. As well, such a PID controller is designed to mate two important frequencies, at which the given system is excited, very close so that an appropriate reference profile generated by using command shaping techniques can cover those two frequencies. Root-locus analysis. which shows traces of closed-loop poles for the given system, is used to design this PID controller. Finally, feedforward controller is added to improve tracking performance of the closed-loop system. Simulation for a system with a flexible mode and parameter uncertainties is executed to prove the feasibility of this technique.