• IE interfaces
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• v.8 no.3
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• pp.241-248
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• 1995

Fa SI(Sysrem Intergration)분야에 있어서 PLC(Programmable Logic Controller)와 컴퓨터간의 접속은 필수 불가결한 요소기술로 자리잡고 있으며, 이러한 기술변화에 맞춰서 기존 유니트의 기술적 발전뿐 아니라 타 유니트와 접속등의 네트워킹에 관련된 내용이 하드웨어, 소트프웨어적으로 발전되고 있는 추세이다. 시스템통합을 하기 위해서는 기본적으로 PLC Networking을 하드웨어, 소프트웨어적으로 수행하여야 하나, 많은 연구들이 PLC 통신 유니트의 기술적 향상 및 표준화에 대한 부분으로 되어왔었다. 본 논문은 정보시스템을 구축할 때 PLC에서 처리하여야 하는 데이터, 혹은 컴퓨터와 송수신 받아야 하는 자료들에 대한 내용과 이들 자료를 PLC 내부에서 처리하는 방법론에 대해 기술코자 한다. 일반적인 Interface 방법으로 접점연결(Point to Point Connection)과 컴퓨터링크유니트에 대한 내용을 파악해보고, 설비고장진단 및 이상발생에 대한 추적이 가능하도록 PLC Memory내에 PLC접점데이타를 직접접근방식(Direct Accssing Method)과 간접접근방식 (Indirect Accssing Method)으로 구분하고, 간접접근방식을 요소(Element), 동작(Event)에 의한 방법론을 이용하여 PLC DATA를 처리토록 하는 내용을 설명하고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• Journal of Auto-vehicle Safety Association
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• v.13 no.4
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• pp.129-143
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• 2021

This paper proposes actuator fault detection and adaptive fault-tolerant control algorithms using performance index and human-like learning for longitudinal autonomous vehicles. Conventional longitudinal controller for autonomous driving consists of supervisory, upper level and lower level controllers. In this paper, feedback control law and PID control algorithm have been used for upper level and lower level controllers, respectively. For actuator fault-tolerant control, adaptive rule has been designed using the gradient descent method with estimated coefficients. In order to adjust the control parameter used for determination of adaptation gain, human-like learning algorithm has been designed based on perceptron learning method using control errors and control parameter. It is designed that the learning algorithm determines current control parameter by saving it in memory and updating based on the cost function-based gradient descent method. Based on the updated control parameter, the longitudinal acceleration has been computed adaptively using feedback law for actuator fault-tolerant control. The finite window-based performance index has been designed for detection and evaluation of actuator performance degradation using control error.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.98-109
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• 2002

Bluetooth technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range :1nd point-to-multipoint voice and data transfer. It operates in the 2.4㎓ ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module with direct memory access method we have developed. This module consists of three blocks; link controller, UART interface, and audio CODEC. This module has a bus interface for data communication between this module and main processor and a RF interface for the transmission of bit-stream between this module and RF module. The bus interface includes DMA interface. Compared with the link controller with FIFOs, The module with DMA has a wide difference in size of module and speed of data processing. The small size module supplies lorr cost and various applications. In addition, this supports a firmware upgrade capability through UART. An FPGA and an ASIC implementation of this module, designed as soft If, are tested for file and bit-stream transfers between PCs.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.4
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• pp.116-128
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• 2011

In this paper, we propose the structure of a high-performance face-detection engine that responds well to facial rotating changes using rotation transformation which minimize the required memory usage compared to the previous face-detection engine. The validity of the proposed structure has been verified through the implementation of FPGA. For high performance face detection, the MCT (Modified Census Transform) method, which is robust against lighting change, was used. The Adaboost learning algorithm was used for creating optimized learning data. And the rotation transformation method was added to maintain effectiveness against face rotating changes. The proposed hardware structure was composed of Color Space Converter, Noise Filter, Memory Controller Interface, Image Rotator, Image Scaler, MCT(Modified Census Transform), Candidate Detector / Confidence Mapper, Position Resizer, Data Grouper, Overlay Processor / Color Overlay Processor. The face detection engine was tested using a Virtex5 LX330 FPGA board, a QVGA grade CMOS camera, and an LCD Display. It was verified that the engine demonstrated excellent performance in diverse real life environments and in a face detection standard database. As a result, a high performance real time face detection engine that can conduct real time processing at speeds of at least 60 frames per second, which is effective against lighting changes and face rotating changes and can detect 32 faces in diverse sizes simultaneously, was developed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of Digital Convergence
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• v.15 no.12
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• pp.323-331
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• 2017

In this paper, four types of deposition control processes such as temperature, pressure, input/output(I/O), and gas were replaced by the Internet of Things(IoT) to analyze the data load and sequence procedure before and after the application of it. Through this analysis, we designed the load balancing in the sensing area of the deposition process by creating the sequence diagram of the deposition process. In order to do this, we were modeling of the sensor I/O according to the arrival process and derived the result of measuring the load of CPU and memory. As a result, it was confirmed that the reliability on the deposition processes were improved through performing some functions of the equipment controllers by the IoT. As confirmed through this paper, by applying the IoT to the deposition process, it is expected that the stability of the equipment will be improved by minimizing the load on the equipment controller even when the equipment is expanded.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.