• Journal of Information Technology Applications and Management
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• v.11 no.2
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• pp.29-43
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• 2004

As the development of an information technique, gradually, mobile device is going to be miniaturized and operates at high speed. By such the requirements, the devices using a flash memory as a storage media are increasing. The flash memory consumes low power, is a small size, and has a fast access time like the main memory. But the flash memory must erase for recording and the erase cycle is limited. JFFS is a representative filesystem which reflects the characteristics of the flash memory. JFFS to be consisted of LSF structure, writes new data to the flash memory in sequential, which is not related to a file size. Mounting a filesystem or an error recovery is achieved through the sequential approach. Therefore, the mounting delay time is happened according to the file system size. This paper proposes a MJFFS to use a multi-checkpoint information to manage a mass flash file system efficiently. A MJFFS, which improves JFFS, divides a flash memory into the block for suitable to the block device, and stores file information of a checkpoint structure at fixed interval. Therefore mounting and error recovery processing reduce efficiently a number of filesystem access by collecting a smaller checkpoint information than capacity of actual files. A MJFFS will be suitable to a mobile device owing to accomplish fast mounting and error recovery using advantage of log foundation filesystem and overcoming defect of JFFS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.23-26
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• 2003

The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1125-1128
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• 1987

This paper proposes a method which distributes the structure data represented by a tree and handles it. To distribute and handle the structure data, this method partitions a structure data and distributes the partitioned structure in multiple processing element and allocates the partitioned structure. Each processing element includes the structure memory to store the partitioned structure and the structure controller to handle efficiently the distributed structure. As the structure is distributed and is stored in the structure memory and is handled by the structure controller, the processing time is reduced.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.69-72
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• 2007

No doubt that more vast data and precise values are required for the detailed and accurate analysis result. People's expectation for the output of space application goes higher, and consequently satellite memory system has to process massive data faster. This paper reviews memory systems of KOMPSAT (Korea Multi-Purpose SATellite) series and try to find a suitable memory system structure to process data more faster not at device level but at system level.

• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.5 s.108
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• pp.408-415
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• 2006

This paper suggests an improved system-level model of RF power amplifiers(PAs) including memory effects, and validates the suggested model by analyzing the power spectral density of the output signal with a predistortion linearizer. The original three-box(Wiener-Hammerstein) model uses input and output filters to capture RF frequency response of PAs. The adjacent spectral regrowth that occurs in three-box model can be perfectly removed by Hammerstein structure predistorter. However, the predistorter based on Hammerstein structure achieves limited performance in real PA applications due to other memory effects except RF frequency response. The spectrum of the output signal can be predicted accurately using the suggested model that changes a memoryless block in a three-box model with a memory polynomial. The proposed model accurately predicts the output spectrum density of PA with Hammerstein structure predistorter with less than 2 dB errors over ${\pm}30$ MHz adjacent channel ranges for IEEE 802.11 g WLAN signal.

• KIPS Transactions on Software and Data Engineering
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• v.7 no.8
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• pp.307-324
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• 2018

Recently, recurrent neural networks have been attracting attention in solving prediction problem of sequential data through structure considering time dependency. However, as the time step of sequential data increases, the problem of the gradient vanishing is occurred. Long short-term memory models have been proposed to solve this problem, but there is a limit to storing a lot of data and preserving it for a long time. Therefore, research on memory-augmented neural network (MANN), which is a learning model using recurrent neural networks and memory elements, has been actively conducted. In this paper, we describe the structure and characteristics of MANN models that emerged as a hot topic in deep learning field and present the latest techniques and future research that utilize MANN.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1433-1442
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• 1996

Data distribution of SPMD(Single Program Multiple Data) pattern is one of main features of HPF (High Performance Fortran). This paper describes design is sues for such data distribution and its efficient execution model on TICOM IV computer, named SPAX(Scalable Parallel Architecture computer based on X-bar network). SPAX has a hierarchical clustering structure that uses distributed shared memory(DSM). In such memory structure, it cannot make a full system utilization to apply unanimously either SMDD(shared Memory Data Distribution) or DMDD(Distributed Memory Data Distribution). Here we propose another data distribution model, called DSMDD(Distributed Shared Memory Data Distribution), a data distribution model based on hierarchical masters-slaves scheme. In this model, a remote master and slaves are designated in each node, shared address scheme is used within a node and message passing scheme between nodes. In our simulation, assuming a node size in which system performance degradation is minimized,DSMDD is more effective than SMDD and DMDD. Especially,the larger number of logical processors and the less data dependency between distributed data,the better performace is obtained.