• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Annual Conference of KIPS
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• 2020.11a
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• pp.20-23
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• 2020

This research is to design an effective prefetching method required for DRAM-PCM hybrid main memory systems especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform well with regular memory access patterns. However, workloads such as graph processing show extremely irregular memory access characteristics and thus could not be prefetched accurately. Therefore, this research proposes an efficient dynamical prefetching algorithm based on the regression method. We have designed an intelligent prefetch engine that can identify the characteristics of the memory access sequences. It can perform regular, linear regression or polynomial regression predictive analysis based on the memory access sequences' characteristics, and dynamically determine the number of pages required for prefetching. Besides, we also present a DRAM-PCM hybrid memory structure, which can reduce the energy cost and solve the conventional DRAM memory system's thermal problem. Experiment result shows that the performance has increased by 40%, compared with the conventional DRAM memory structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.148-155
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• 2006

Portable embedded systems which mainly handle multimedia applications involve the problem that frequent accesses to fetch data from memory make running time increased. To cope with the problem, embedded processors have adopted data prefetching schemes. From a power point of view, which is a main performance indicator of embedded systems, this paper analyzed to investigate how data prefetching schemes influence on system's performance. To solve the problem, we proposed a power-consumption analysis model of a memory system with data prefetching scheme and measured the power dissipated during running application programs. As a result data prefetching schemes have application program's running time reduced but have system's power increased. Also we proposed a performance analysis model considering execution time and power consumption for embedded system with data prefetching schemes.

• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.406-412
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• 2001

IP address lookup is to determine the next hop destination of an incoming packet in the router. The address lookup is a major bottleneck in high performance router due to the increased routing table sizes, increased traffic, higher speed links, and the migration to 128 bits IPv6 addresses. IP lookup time is dependent on data structure of lookup table and search scheme. In this paper, we propose a new approach to build a lookup table that satisfies the memory constraint. The design of lookup table is formulated as an optimization problem. The objective is to minimize average depth from the root node for lookup. We assume that the frequencies with which prefixes are accessed are known and the data structure is level compressed trie with branching factor $\kappa$ at the root and binary at all other nodes. Thus, the problem is to determine the branching factor k at the root node such that the average depth is minimized. A heuristic procedure is proposed to solve the problem. Experimental results show that the lookup table based on the proposed heuristic has better average and the worst-case depth for lookup.

• Bulletin of the Korean Mathematical Society
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• v.61 no.1
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• pp.161-193
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• 2024

In this paper, we consider the asymptotic behavior of solutions for the partly dissipative reaction diffusion systems of the FitzHugh-Nagumo type with hereditary memory and a very large class of nonlinearities, which have no restriction on the upper growth of the nonlinearity. We first prove the existence and uniqueness of weak solutions to the initial boundary value problem for the above-mentioned model. Next, we investigate the existence of a uniform attractor of this problem, where the time-dependent forcing term h ∈ L²_b(ℝ; H^-1(ℝ^N)) is the only translation bounded instead of translation compact. Finally, we prove the regularity of the uniform attractor A, i.e., A is a bounded subset of H²(ℝ^N) × H¹(ℝ^N) × L²_µ(ℝ⁺, H²(ℝ^N)). The results in this paper will extend and improve some previously obtained results, which have not been studied before in the case of non-autonomous, exponential growth nonlinearity and contain memory kernels.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.8
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• pp.1004-1009
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• 2014

The redundancy allocation problem has usually considered only the component redundancy at the lowest-level for the enhancement of system reliability. A system can be functionally decomposed into system, module, and component levels. Modular redundancy can be more effective than component redundancy at the lowest-level because in modular systems, duplicating a module composed of several components can be easier, and requires less time and skill. We consider a multi-level redundancy allocation problem in which all cases of redundancy for system, module, and component levels are considered. A tabu search of memory-based mechanisms that balances intensification with diversification via the short-term and long-term memory is proposed for its solution. To the best of our knowledge, this is the first attempt to use a tabu search for this problem. Our tabu search algorithm is compared with the previous genetic algorithm for the problem on the new composed test problems as well as the benchmark problems from the literature. Computational results show that the proposed method outstandingly outperforms the genetic algorithm for almost all test problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.85-91
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• 2012

In this paper, the large data processing and suitable FAT32 file system for industrial system using a PLC and CF memory was implemented. Most of PLC can't save the large data in user data memory. So it's required to the external devices of CF memory or NAND flash memory. The CF memory is used in order to save the large data of PLC system. The file system using the CF memory is NTFS, FAT, and FAT32 system to configure in various ways. Typically, the file system which is widely used in industrial data storage has been implemented as modified FAT32. The conventional FAT 32 file system was not possible for multiple writing and high speed data accessing. The proposed file system was implemented by the large data processing module can be handled that the files are copied at the 40 bytes for 1msec speed logging and creating 8 files at the same time. In a sudden power failure, high reliability was obtained that the problem was solved using a power fail monitor and the non-volatile random-access memory (NVSRAM). The implemented large data processing system was applied the modified file system as FAT32 and the good performance and high reliability was showed.

• Computational Structural Engineering
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• v.4 no.2
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• pp.103-110
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• 1991

To solve the large problems with limited core memory of computer, a disk management scheme called virtual memory database has been developed. Utilizing this technique along with memory moving scheme, an efficient in-and out-of-core column solver for the sparse symmetric matrix commonly arising in the finite element analysis is developed. Compared with other methods the algorithm is simple, therefore the coding and computational efficiencies are greatly enhanced. Analysis example shows that the proposed method efficiently solve the large structural problem on the small-memory micro-computer.

• Journal of the Korea Computer Industry Society
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• v.6 no.2
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• pp.295-304
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• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.