• Title/Summary/Keyword: Memory Problem

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Reducing Memory Requirements of Multidimensional CMAC Problems (고차원 CMAC 문제의 소요 기억량 감축)

  • 권성규
    • Journal of the Korean Institute of Intelligent Systems
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    • v.6 no.3
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    • pp.3-13
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    • 1996
  • In orde to reduce huge memory requirements of multidimensional CMAC problems, building a CMAC system by problem decomposition is investigated. Decomposition is based on resolving a displacement vector in cartesian coordinates into unit vectors that define a few lower-dimensional CMACs in the CMAC system. A CMAC system for an an in verse kinematics problem for a planar manipulator was simulated and the performance of the system was evaluated in terms of training and output quality.

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The Early Write Back Scheme For Write-Back Cache (라이트 백 캐쉬를 위한 빠른 라이트 백 기법)

  • Chung, Young-Jin;Lee, Kil-Whan;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.101-109
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    • 2009
  • Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

Development of Flash Memory Page Management Techniques

  • Kim, Jeong-Joon
    • Journal of Information Processing Systems
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    • v.14 no.3
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    • pp.631-644
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    • 2018
  • Many studies on flash memory-based buffer replacement algorithms that consider the characteristics of flash memory have recently been developed. Conventional flash memory-based buffer replacement algorithms have the disadvantage that the operation speed slows down, because only the reference is checked when selecting a replacement target page and either the reference count is not considered, or when the reference time is considered, the elapsed time is considered. Therefore, this paper seeks to solve the problem of conventional flash memory-based buffer replacement algorithm by dividing pages into groups and considering the reference frequency and reference time when selecting the replacement target page. In addition, because flash memory has a limited lifespan, candidates for replacement pages are selected based on the number of deletions.

The Effect of Cognitive Rehabilitation Program for Traumatic Brain Injury Patients (외상성 뇌손상 환자를 위한 인지재활 프로그램의 효과)

  • Park, Joon-Ho;Jung, Han-Yong;Lee, SoYoung Irene
    • Korean Journal of Biological Psychiatry
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    • v.9 no.2
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    • pp.120-128
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    • 2002
  • Objectives:The purpose of this study was to develop a cognitive rehabilitation program and to investigate the effect of the program that restores the deficiency of memory, which is necessary to operate on high cognitive function such as problem-solving or judgement, for TBI(traumatic brain injury) patients. Methods:Sixteen TBI patients participated in this study. The inclusion criteria were : 1) aged 18 to 60 ; 2) higher than IQ 80 ; 3) lower than MMSE-K 25 and K-MAS(Korean version of Memory Assessment Scale) 85. We administered our program to an experimental group(N=8) in order to improve attention and memory for 4 weeks(total 12 section). Our program was not administrated to a control group(N=8) for 4 weeks. After administrating this program, we measured MMSE-K and K-MAS for the experimental and control groups. Results:The findings of the study were as follows. 1) the experimental group showed significant improvement on MMSE-K score in comparison with baseline, but the control group did not. 2) the experimental group showed significant improvement on K-MAS score in comparison with baseline, but the control group did not. In particular, among the three subscales of K-MAS, only verbal memory scale revealed significant improvement, while visual and short-term memory scales revealed no differences. Conclusion:Our cognitive rehabilitation program improves cognitive state and memory, particulary verbal memory, for TBI patients. These results imply that our program aids in rehabilitation of basic cognition such as memory which is necessary to operate on high cognitive function such as problem-solving or judgement, for TBI(traumatic brain injury) patients.

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Memory Effect of $In_2O_3$ Quantum Dots and Graphene in $SiO_2$ thin Film

  • Lee, Dong Uk;Sim, Seong Min;So, Joon Sub;Kim, Eun Kyu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.240.2-240.2
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    • 2013
  • The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

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GPU Memory Management Technique to Improve the Performance of GPGPU Task of Virtual Machines in RPC-Based GPU Virtualization Environments (RPC 기반 GPU 가상화 환경에서 가상머신의 GPGPU 작업 성능 향상을 위한 GPU 메모리 관리 기법)

  • Kang, Jihun
    • KIPS Transactions on Computer and Communication Systems
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    • v.10 no.5
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    • pp.123-136
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    • 2021
  • RPC (Remote Procedure Call)-based Graphics Processing Unit (GPU) virtualization technology is one of the technologies for sharing GPUs with multiple user virtual machines. However, in a cloud environment, unlike CPU or memory, general GPUs do not provide a resource isolation technology that can limit the resource usage of virtual machines. In particular, in an RPC-based virtualization environment, since GPU tasks executed in each virtual machine are performed in the form of multi-process, the lack of resource isolation technology causes performance degradation due to resource competition. In addition, the GPU memory competition accelerates the performance degradation as the resource demand of the virtual machines increases, and the fairness decreases because it cannot guarantee equal performance between virtual machines. This paper, in the RPC-based GPU virtualization environment, analyzes the performance degradation problem caused by resource contention when the GPU memory requirement of virtual machines exceeds the available GPU memory capacity and proposes a GPU memory management technique to solve this problem. Also, experiments show that the GPU memory management technique proposed in this paper can improve the performance of GPGPU tasks.

The influence of sleep and sleep apnea on memory function (수면 무호흡과 수면이 기억기능에 미치는 영향)

  • Lee, Sung-Hoon;Lee, Na-Young;Park, Yun-Jo;Jon, Duk-In
    • Sleep Medicine and Psychophysiology
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    • v.5 no.2
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    • pp.177-184
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    • 1998
  • Objectives : Disturbance of sleep with or without sleep apnea may impair the memory function. Sleep deficiency, sleepiness, sleep apnea and emotional problem in sleep disorders can induce an impairment of memory function. Methods : In this study, the polysomnographies were administered to 58 sleep apnea patients and 38 sleep disorder patients without sleep apnea. Their clinical symptoms were quantitatively evaluated. Short term and long term memory were evaluated before and after polysom no graphy with Digit symbol test and Rey-Osterrieth complex figure test. And correlations among various sleep, repiratory and clinical variables were statistically studied in order to explore which variables may influence on memory function. Results and Conclusions : Results are as follows. Depth of sleep cis positively correlated with memory function. As sleep apnea increases and average saturation of blood oxygen decreases, memory function is more impaired. Emotional depression, high blood pressure, obesity or alcohol impaired memory function. However, daytime sleepiness was not significantly correlated with memory function. The possible mechanisms how above factors influence on the memory function were discussed.

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Development of a Flash Memory Drive for ATA bus (ATA 버스 방식을 위한 Flash Memory Drive 개발)

  • Kang, Kyung-Sik;Jang, Moon-Kee;Hwang, Yeon-Bum;Jung, Nam-Mo;Park, Jin-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.547-550
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    • 2005
  • This treatise studies and developed flash memory drive of ATA bus that use flash memory which is employment amount memory semiconductor to improve problem of hard-disk that is existing ATA bus. While general hard-disk is sensitive external impact or shock, but flash memory drive do save chapter as well as is strong in external impact using semiconductor memory element that disk is not low electric power, light weight possible . Practical use is expected do save chapter for embedded system or black box for vehicles, soldiers hereafter therefore.

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A Psychological Model for Mathematical Problem Solving based on Revised Bloom Taxonomy for High School Girl Students

  • Hajibaba, Maryam;Radmehr, Farzad;Alamolhodaei, Hassan
    • Research in Mathematical Education
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    • v.17 no.3
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    • pp.199-220
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    • 2013
  • The main objective of this study is to explore the relationship between psychological factors (i.e. math anxiety, attention, attitude, Working Memory Capacity (WMC), and Field dependency) and students' mathematics problem solving based on Revised Bloom Taxonomy. A sample of 169 K11 school girls were tested on (1) The Witkin's cognitive style (Group Embedded Figure Test). (2) Digit Span Backwards Test. (3) Mathematics Anxiety Rating Scale (MARS). (4) Modified Fennema-Sherman Attitude Scales. (5) Mathematics Attention Test (MAT), and (6) Mathematics questions based on Revised Bloom Taxonomy (RBT). Results obtained indicate that the effect of these items on students mathematical problem solving is different in each cognitive process and level of knowledge dimension.

Bit Flip Reduction Schemes to Improve PCM Lifetime: A Survey

  • Han, Miseon;Han, Youngsun
    • IEIE Transactions on Smart Processing and Computing
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    • v.5 no.5
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    • pp.337-345
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    • 2016
  • Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.