• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.39-42
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• 2001

This paper proposes the design technique of memory sparing to overcome memory hard error Memory Sparing is used to increase the reliability and availability of commercial, military and space computer such as a Data Server, Communication Server, Flight Computer in airplane and On-Board Computer in spacecraft. But the documents about this technique are rare and hard to find. This paper has some useful information about memory error correction and memory error management.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• International Journal of Knowledge Content Development & Technology
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• v.5 no.2
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• pp.75-101
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• 2015

In this paper, we investigate the notion of error correction memory applied to technical texts. The main purpose is to introduce flexibility and context sensitivity in the detection and the correction of errors related to Constrained Natural Language (CNL) principles. This is realized by enhancing error detection paired with relatively generic correction patterns and contextual correction recommendations. Patterns are induced from previous corrections made by technical writers for a given type of text. The impact of such an error correction memory is also investigated from the point of view of the technical writer's cognitive activity. The notion of error correction memory is developed within the framework of the LELIE project an experiment is carried out on the case of fuzzy lexical items and negation, which are both major problems in technical writing. Language processing and knowledge representation aspects are developed together with evaluation directions.

• Journal of information and communication convergence engineering
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• v.19 no.1
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• pp.22-28
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• 2021

Convolutional neural networks (CNNs) are one of the most frequently used artificial intelligence techniques. Among CNN-based applications, small and timing-sensitive applications have emerged, which must be reliable to prevent severe accidents. However, as the small and timing-sensitive systems do not have sufficient system resources, they do not possess proper error protection schemes. In this paper, we propose MATE, which is a low-cost CNN weight error correction technique. Based on the observation that all mantissa bits are not closely related to the accuracy, MATE replaces some mantissa bits in the weight with error correction codes. Therefore, MATE can provide high data protection without requiring additional memory space or modifying the memory architecture. The experimental results demonstrate that MATE retains nearly the same accuracy as the ideal error-free case on erroneous DRAM and has approximately 60% accuracy, even with extremely high bit error rates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.655-658
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• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.185-190
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• 2007

The necessity of error test module is increasing as development of embedded Linux device driver. This paper proposes the basic concept of freed memory error test module in the Linux device driver and designs error test module. The USB device driver is designed for freed memory error test module. I insert the test code to verify the USB device driver. I test the suggested error test module for the USB storage device driver. I experiment error test in this module.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.601-606
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• 2017

SRAM-based FPGAs mainly used to develop and implement high-performance circuits have SRAM-type configuration memory. Soft errors in memory devices are the main threat from a reliability point of view. Soft errors occurring in the configuration memory of FPGAs cause FPGAs to malfunction. SEM(Soft Error Mitigation) Controllers offered by Xilinx can mitigate the influence of soft errors in configuration memory. SEM Controllers use ECC(Error Correction Code) and CRC(Cyclic Redundancy Code) which are placed around the configuration memory to detect and correct the errors. The correction is done through a partial reconfiguration process. This paper presents the availability analysis of SRAM-based FPGAs against soft errors under the protection of SEM Controllers. Availability functions were derived and compared according to the correction capability of SEM Controllers of several different families of FPGAs. The result may help select an SRAM-based FPGA part and estimate the availability of FPGAs running in an environment where soft errors occur.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.61-68
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• 2011

Memory error debugging is one of the most critical processes in improving software quality. However, due to the extensive time consumed to debug, the enhancement often leads to a huge bottle neck in the development process of mobile devices. Most of the existing memory error detection tools are based on static error detection; however, the tools cannot be used in mobile devices due to their use of large working memory. Therefore, it is challenging for mobile device vendors to deliver high quality mobile devices to the market in time. In this paper, we introduce "PinMemcheck", a pin-based memory error detection tool, which detects all potential memory errors within $1.5{\times}$ execution time overhead compared with that of a baseline configuration by applying the Pin's binary instrumentation process and a simple data structure.