• Journal of KIISE:Software and Applications
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• v.34 no.6
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• pp.562-571
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• 2007

Various researches had been devoted in purpose of improving memory management in terms of performance, efficiency, ease of use, and safety. One of these approaches is a region-based memory management. Each allocation site selects a specific region, after that allocated objects are placed in this region. Memory is reclaimed by destroying the region, freeing all the objects allocated therein. In this paper, we propose reusing of local regions to reduce heap memory usage in memory-limited environments. The basic idea of this proposal is reusing of upper local regions where objects that are allocated to these regions are not accessed until the current method is finished. We believe our method of reusing local regions is able to overcome memory constraints in memory-limited environments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.801-804
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• 2009

In this paper, the Linux kernel memory map was analyzed as the approach to Improving performance for Embedded Linux system. Since the Linux kernel memory map supporting a stability and various H/W platforms and in which it becomes to the general purpose system with optimization manages the role of being important in the booting time and the efficient system utilization of resources, the analysis of the kernel memory map is required for the performance improvement of the Embedded Linux system in which it is restrictive the resources. According to the analysis result, and of the Linux kernel memory, the booting speed of and improvement of the memory efficiency were confirmed. It is therefore considered that the proposed in this paper and kernel memory allocation method are suitable to the memory availability improvement of the Embedded Linux system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.395-396
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• 2008

There is difficulty in predicting the program efficiency of NOR type nonvolatile memory device adopting channel hot electron injection (CHEI) as program operation mechanism accurately since MOSFET on SOI has floating body. In this study, the dependence of program efficiency for SOI nonvolatile memory device of 200 nm channel length on SOI depletion conditions, partial depletion and full depletion, was quantitatively investigated with the aid of numerical device simulation [1].

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.11
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• pp.810-819
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• 2006

This paper proposes an Adaptive Double Buffer Model. As a new FIFO buffer model, this technique minimizes packet losses from network congestion by logically managing buffers. It allocates the spare spaces of non-congested buffers to congested buffers by allowing receive/send buffers to share two queues, and hence it minimizes packet losses. In contrast to the buffer model utilizing a free list, this buffer model can prevent the bubble phenomenon caused by a memory leak and thereby apply to a network buffer in a restricted environment. Also, compared with the model using an way, this model brings maximum 100 percent improvement in accepting packets and compared with the model utilizing a free list, this model has the similar efficiency Results of the performance test on Adaptive Double Buffer Model, shows that this proposed model decreases packet losses and enhances memory efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.19-26
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• 2009

Recently, the Main Memory DBMS is gradually being expanded by the appearance of a large capacity of a Main Memory System, the increase in business area where it requires a real time process, and the rise of the users' required level. The Main Memory DBMS, which is able to go through a large capacity data process of the disk-based DBMS and guarantees a high efficiency, has domestically developed and has been put to a practical use. This paper presents an examination of the applied technologies and the limits of Altibase system, which is Main Memory DBMS. Moreover, it evaluated and performed a comparative analysis on the performance level of the Main Memory DBMS and the disk-based DBMS based on the same application. After five trials of the experiment based on the operating application, it was confirmed that the performance level of the Main Memory DBMS is enhanced and is higher by 4.13 to 7.89 times than the disk-based DBMS.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.405-412
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• 2002

The embedded system has less fast CPU and lower memory than PC(personal Computer) or Workstation system. Therefore embedded operating is system is designed to efficiently use the limited resource in the system. Virtual memory management or the embedded linux have a low efficiency when page fault is occurred to get a data from I/O device. Because a data is moving from the swap device to main memory. This paper suggests virtual memory compression algorithm for improving in virtual memory management and capacity of space. In this paper, we present a way to performance implement a virtual memory compression system that achieves significant improvement for the embedded system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.491-492
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• 2008

According to high-speed large scale integration trend of Memory module product, many type of noises, such a reflection, cross-talk simultaneous switching noise, occur on the Package PCB and they make the deterioration of memory module's performance and reliability. As module products have more high efficiency, Hardware of test board and socket has to be considered In test of the high-speed Memory Module. we mainly focused on improvement of Signal integrity Using the High Frequency Test socket that we invented

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.4
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• pp.192-200
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• 2001

As the high density memory is widely used in the various applications, the need for reproduction of memory is increased. In this paper we propose an efficient fault diagnosis algorithm of linear order O(n) that enables the reproduction of memory. The new algorithm can distinguish various fault models and identify all the cells related to the faults. In addition, a new BIST architecture for fault diagnosis is developed. Using the new algorithm, fault diagnosis can be performed efficiently. And the performance evaluation with previous approaches proves the efficiency of the new algorithm.