• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Molecules and Cells
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• v.39 no.7
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• pp.515-523
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• 2016

Long-term immunity to many viral and bacterial pathogens requires$ CD8^+$ memory T cell development, and the induction of long-lasting$ CD8^+$ memory T cells from a $na{\ddot{i}}ve$, undifferentiated state is a major goal of vaccine design. Formation of the memory$ CD8^+$ T cell compartment is highly dependent on the early activation cues received by $na{\ddot{i}ve}$ $CD8^+$ T cells during primary infection. This review aims to highlight the cellularity of various niches within the lymph node and emphasize recent evidence suggesting that distinct types of T cell activation and differentiation occur within different immune contexts in lymphoid organs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.706-711
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• 2012

Multi-level cell NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored. Currently, most multi-level cell NAND stores 2 bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The most error cause is coupling noise. Thus, in this paper, we studied coupling noise cancellation scheme for reduction memory on the 16-level cell NAND flash memory channel. Also, we compared the performance threshold detection and proposed scheme.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.894-897
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• 2006

Spatial distribution of injected electrons and holes is evaluated by using single-junction charge pumping technique in SONOS(Poly-silicon/Oxide/Nitride/Oxide/Silicon) memory cells. Injected electron are limited to length of ONO(Oxide/Nitride/oxide) region in locally ONO stacked cell, while are spread widely along with channel in fully ONO stacked cell. Hot-holes are trapped into the oxide as well as the ONO stack in locally ONO stacked cell.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.253-261
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• 2008

Programmable metallizaton cell (PMC) memory device has been known as one of the next generation non-volatile memory devices, because it includes non-volatility, high speed and high ON/OFF resistance ratio. This paper reviews the operation principle of the device. Besides, the recent research results of professor Kozicki who firstly invented the device and investigated it for the memory applications, NEC corporation which studied it for the FPGA (field programmable gate array) switch applications, ETRI and chungnam national university which examined Te-based devices are introduced.

• Biomedical Science Letters
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• v.28 no.4
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• pp.211-222
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• 2022

After more than two years of efforts to end the corona pandemic, a gradual recovery is starting in countries with high vaccination rates. Easing public health policies for a full-fledged post-corona era, such as lifting the mandatory use of outdoor mask and quarantine measures in entry have been considered in Korea. However, the continuous emergence of new variants of SARS-CoV-2 and limitations in vaccine efficacy still remain challenging. Fortunately, T cells and memory T cells, which are key components of adaptive immunity appear to contribute substantially in COVID-19 control. SARS-CoV-2 specific CD4⁺/CD8⁺ T cells are induced by natural infection or vaccination, and rapid induction and activation of T cells is mainly associated with viral clearance and attenuated clinical severity. In addition, T cell responses induced by recognition of a wide range of epitopes were minimally affected and conserved against the highly infectious subsets of omicron variants. Polyfunctional SARS-CoV-2 specific T cell memory including stem cell-like memory T cells were also developed in COVID-19 convalescent patients, suggesting long lasting protective T cell immunity. Thus, a robust T-cell immune response appears to serve as a reliable and long-term component of host protection in the context of reduced efficacy of humoral immunity and persistent mutations and/or immune escape.