• Journal of Digital Convergence
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• v.10 no.4
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• pp.243-250
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• 2012

This study proposes new protocol protecting patients' personal record more safely as well as solving medical dispute smoothly by storing the record not into a computer server in hospitals but into the National Health Insurance Corporation computer server. The new protocol for electronic medical record is designed using RSA public key algorithm and DSA digital signature. In addition, electronic medical record systems are built up with more safety and reliability through certificate authority. The proposed medical information systems can strengthen trust between doctors and patients. If medical malpractice occurs, the systems can also provide evidence. Furthermore, the systems can be helpful to reduce medical accidents. The systems could be also utilized efficiently in various applied areas.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.937-944
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• 2002

The current fast-growing Internet traffic is demanding more and more network capacity. Photonic packet switching offers high-speed, data rate/format transparency, and configurability, which are some of the important characteristics needed in future networks supporting different forms of data. In this paper, we define that optical backbone networks for IP transport consist of optical packet core switches and optical fibers. We propose a multi-link photonic packet switch managing as single media which unifies the whole bandwidth of multiple wavelengths on the optical fiber in the WDM optical networks. The proposed switch uses optical packet memories of output link equally as well as using the WDM buffer. So it cuts down the required number of buffers and realizes of the optical packet memory economically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.117-124
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• 1998

As window sized increases, the throughput input-buffered packet switch with a window scheme improves on random traffic condition. However, the improvement diminishes quickly under bursty traffic. In this paper, we propose Burst Head Addressable FIFO mechanism and memory structure having search capability in unit of burst header to compensate the sensitiveness of the windowed scheme to bursty traffic. The performance of a input-buffered switch using the proposed Burst Header Addressable FIFO input buffer was analyzed using computer simulations. The maximum throughput of the conventional FIFO scheme approaches an asymptotic value 0.5 as mean burst length increases. The maximum throughput of the proposed scheme is greater than that of the conventional scheme for any mean burst length and window size.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.579-585
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• 2003

Recently most of 3D graphics rendering Processors have the pixel cache storing depth data and color data to reduce the memory latency and the bandwidth requirement. In this paper, we propose the effective pixel cache for improving the performance of a rendering processor. The proposed cache system stores the depth data selectively based on the result of Z-test and the color data are stored into the auxiliary buffer. Simulation results show that the 16Kbyte proposed cache system provides better performance than the 32Kbyte conventional cache.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$ thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$ film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$ thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$ to YMnO$_3$ was 1.83. As a XPS analysis, the surface of etched CeO$_2$ thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.213-219
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• 2004

This paper describes the developmnet of a web-based boiler controller which can be in parallel operated with an existing boiler controller. The web-based boiler controller mainly consists of RTL8019AS NIC and TS80C32 microcontroller. In order to communicate over the Internet, we need to develop network driver, IP, TCP, UDP, ICMP, and HTTP. For a specific application like web-boiler controller, we have proposed a common global data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using CommView and Dummynet. The development is satisfactorily operated only for few hundreds of bytes of RAM usage without sacrificing interoperability between hosts.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.2
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• pp.153-166
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• 2020

DDI(Display Driver IC) are used to drive numerous pixels that make up display. For stable driving of DDI, it is necessary to attach a protective film to shield electromagnetic waves. When the protective film is attached, defects often occur if the film is inclined or the center point is not aligned. In order to minimize such defects, an algorithm for correcting the center point and the inclined angle using camera image information is required. This technology detects the corner coordinates of the protective film by image processing in order to correct the positional defects where the protective film is attached. Corner point coordinates are detected using an algorithm, and center point position finds and correction values are calculated using the detected coordinates. LUT (Lookup Table) is used to quickly find out whether the angle is inclined or not. These algorithms were described by Verilog HDL. The method using the existing software requires a memory to store the entire image after processing one image. Since the method proposed in this paper is a method of scanning by adding a line buffer in one scan, it is possible to scan even if only a part of the image is saved after processing one image. Compared to those written in software language, the execution time is shortened, the speed is very fast, and the error is relatively small.