• Journal of electromagnetic engineering and science
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• v.10 no.2
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• pp.73-77
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• 2010

This paper proposes a novel memory effect measurement technique in RF power amplifiers(PAs) using a two-tone intermodulation distortion(IMD) signal with a very simple and intuitive algorithm. Based on the proposed predistortive tone cancellation technique, the proposed measurement method is capable of measuring the relative phase and magnitude of the third-order and fifth-order IMDs, as well as the fundamental signal. The measured relative phase between the higher and lower IMD signal for specific tone spacing can be interpreted as the group delay(GD) information of the IMD signal concerned. From the group delay analysis, we can conclude that an adaptive control of GD as well as the magnitude and phase is a key function in increasing the linearization bandwidth and the dynamic range in a predistortion(PD) technique.

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.13-24
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• 2003

Grid technology requires use of geographically distributed resources from multiple domains. Resource monitoring services or tools consisting sensors or agents will run on many systems to find static resource information (such as architecture vendor, OS name and version, MIPS rate, memory size, CPU capacity, disk size, and NIC information) and dynamic resource information (CPU usage, network usage(bandwidth, latency), memory usage, etc.). Thus monitoring itself may cause system overhead. This paper proposes the optimal monitoring interval to reduce the cost of monitoring services and the dynamic monitoring interval to measure monitoring events accurately. By employing two features, we find out unnecessary system overhead is significantly reduced and accuracy of events is still acquired.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.207-224
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• 2010

This paper presents a compression scheme for mesh geometry, which is suitable for mobile graphics. The main focus is to enable real-time decoding of compressed vertex positions while providing reasonable compression ratios. Our scheme is based on local quantization of vertex positions with mesh partitioning. To prevent visual seams along the partitioning boundaries, we constrain the locally quantized cells of all mesh partitions to have the same size and aligned local axes. We propose a mesh partitioning algorithm to minimize the size of locally quantized cells, which relates to the distortion of a restored mesh. Vertex coordinates are stored in main memory and transmitted to graphics hardware for rendering in the quantized form, saving memory space and system bus bandwidth. Decoding operation is combined with model geometry transformation, and the only overhead to restore vertex positions is one matrix multiplication for each mesh partition. In our experiments, a 32-bit floating point vertex coordinate is quantized into an 8-bit integer, which is the smallest data size supported in a mobile graphics library. With this setting, the distortions of the restored meshes are comparable to 11-bit global quantization of vertex coordinates. We also apply the proposed approach to compression of vertex attributes, such as vertex normals and texture coordinates, and show that gains similar to vertex geometry can be obtained through local quantization with mesh partitioning.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.288-299
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• 1993

This paper proposes the new bus protocol in the tightly coupled multiprocessor system. The bus protocol uses the pipelined data transfer and block transfer scheme to increase the bus bandwidth, The bus also has the independent transfer lines for the address and data respectively, and it can transfer the data up to maximum 264 Mbytes /sec. This paper also models the multiprocessor system where each processor boards have the private cache. Simulation evaluates the bus and system performance according to hit ratio of the reference data in cache memory, In the case of using this bus, the bus is evaluated not to be saturated when up to 10 processor boards are connected to the bus. As for up to 4 memory interleavng, the performance increases linearly.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.2914-2935
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• 2016

With the increasing popularization of cloud computing, how to reduce physical energy consumption and increase resource utilization while maintaining system performance has become a research hotspot of virtual machine deployment in cloud platform. Although some related researches have been reported to solve this problem, most of them used the traditional heuristic algorithm based on greedy algorithm and only considered effect of single-dimensional resource (CPU or Memory) on energy consumption. With considerations to multi-dimensional resource utilization, this paper analyzed impact of multi-dimensional resources on energy consumption of cloud computation. A multi-dimensional resource constraint that could maintain normal system operation was proposed. Later, a novel virtual machine deployment method (NVMDM) based on improved particle swarm optimization (IPSO) and Euclidean distance was put forward. It deals with problems like how to generate the initial particle swarm through the improved first-fit algorithm based on resource constraint (IFFABRC), how to define measure standard of credibility of individual and global optimal solutions of particles by combining with Bayesian transform, and how to define fitness function of particle swarm according to the multi-dimensional resource constraint relationship. The proposed NVMDM was proved superior to existing heuristic algorithm in developing performances of physical machines. It could improve utilization of CPU, memory, disk and bandwidth effectively and control task execution time of users within the range of resource constraint.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.371-377
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• 2008

Recently the performance of GPU is increasing much faster compared to GPU and GPU is used for various application programs. In this paper, MPEG-2 Decoder is implemented based on a GPU programming language, CG. The proposed methodology is to perform block rendering with texture data according to video standard with very high parallelism by using the pipeline of GPU which is a stream processing structure. To reduce the data bandwidth between system memory and GPU, local memory is used for graphic card. According to the experiment, the proposed scheme shows performance improvement by more than 2 times compared to CPU based scheme.

• Journal of Internet Computing and Services
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• v.4 no.4
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• pp.65-74
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• 2003

Recently, It is required that multimedia data display on not only PC but also the Mobile device such as cellar phone, PDA. Mobile divieces has not sufficient of storage space or main memory and has slow network speed. So we can't process the multimedia data with the existing way on PC. This paper presents various methods for MultimediaPresentation which are able to display on the mobile device with the low-bandwidth and small storage. There Is an analysis that Is playable on the mobile device using presentation area devision method and replayable analysis method. If the display of multimedia presentation is impossible from this analysis, to apply prefetch techniques a using EPOB apoint and as User QoS of multimedia data through prefetch techniques have keep, do so that playable. Then, it is proposed to playable smooth multimedia presentation as that each of the presentations through prefetch Scheduling techniques point and quantity of data which are prefetch.

• Journal of Korea Society of Industrial Information Systems
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• v.15 no.2
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• pp.31-39
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• 2010

VoD(Video-on-Demand) servers have to provide timely processing guarantees for continuous media and reduce the storage and bandwidth requirements for continuous media. The compression techniques make the bit rates of compressed video data significantly variable from frame to frame. A VoD system should be able to provide the client with interactive operations such as fast forward and fast rewind in addition to normal playback of movie. However, interactive operations require additional resources such as storage space, disk bandwidth, memory and network bandwidth. In a stored video application such as VoD system, it is possible that a priori disk access patterns can be used to reserve the system resources in advance. In addition, clients of VoD server spend most of their time in playback mode and the period of time spent in interactive mode is relatively small. In this paper, I present the new buffer management scheme that provides efficient support for interactive operations in a VoD server using variable bit rate continuous media. Simulation results show that our strategy achieves 34% increase of the number of accepted clients over the LRU strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.