• Title/Summary/Keyword: Memory B cell

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Effects of Treadmill Exercise on Memory, Hippocampal Cell Proliferation, BDNF, TrkB, and Forebrain Cholinergic Cells in Adolescent Rats (트레드밀 운동이 청소년기 흰쥐의 기억력과 해마 신경세포생성, BDNF, TrkB, 그리고 전뇌 콜린 세포에 미치는 영향)

  • Lee, Hee-Hyuk
    • Journal of Life Science
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    • v.19 no.3
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    • pp.403-410
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    • 2009
  • This study investigated the effects of treadmill exercise on memory ability, cell proliferation, BDNF, and TrkB in the hippocampus and forebrain cholinergic cells in adolescent rats. Male Sprague-Dawley rats (4 weeks old) were randomly assigned to the following two groups: the sedentary group (n=10) and the exercise group (n=10). Rats in the exercise group were forced to run on a treadmill for 30 min, five times per week for 4 weeks. The latency of the step-through avoidance task was used in order to evaluate memory ability. Hippocampal brain-derived neurotrophic factor (BDNF) and tropomyosin-related kinase B (TrkB) expression were assessed by Western blotting. Hippocampal cell proliferation and forebrain cholinergic cells were assessed by immunohistochemistry. The present study showed that treadmill running during the adolescent period significantly improved memory capability, increased hippocampal cell proliferation, up-regulated hippocampal BDNF and TrkB expression, and enhanced the number of forebrain cholinergic cells. These results suggest that regular exercise during the adolescent period may enhance memory function.

Design of a 512b Multi-Time Programmable Memory IPs for PMICs (PMIC용 512비트 MTP 메모리 IP설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.1
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    • pp.120-131
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    • 2016
  • In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

New nonvolatile unit memory cell and proposal peripheral circuit using the polymer material (폴리머 재료를 이용한 새로운 비휘발성 단위 메모리 셀과 주변회로 제안)

  • Kim, Jung-Ha;Lee, Sang-Sun
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.825-828
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    • 2005
  • In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.

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A Study on the Characteristics and Programming Conditions of the Scaled SONOSFET NVSM for Flash Memory (플래시메모리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구)

  • 박희정;박승진;남동우;김병철;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.11
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    • pp.914-920
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    • 2000
  • When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

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The study on cell Vth distibution induced by heavily doped channel ionn and Si-SiN stress in flash memory cell (과도한 채널 이온 주입 농도 및 Si-SiN 스트레스가 플래쉬 메모리셀 산포에 미치는 영향)

  • Lee Chi-Kyoung;Park Jung-Ho;Kim Han-Su;Park Kyu-Charn
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.485-488
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    • 2004
  • As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

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Effect of Node Size on the Performance of the B+-tree on Flash Memory (플래시 메모리 상에서 B+-트리 노드 크기 증가에 따른 성능 평가)

  • Park, Dong-Joo;Choi, Hae-Gi
    • The KIPS Transactions:PartA
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    • v.15A no.6
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    • pp.325-334
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    • 2008
  • Flash memory is widely used as a storage medium for mobile devices such as cell phones, MP3 players, PDA's due to its tiny size, low power consumption and shock resistant characteristics. Additionally, some computer manufacturers try to replace hard-disk drives used in Laptops or personal computers with flash memory. More recently, there are some literatures on developing a flash memory-aware $B^+$-tree index for an efficient key-based search in the flash memory storage system. They focus on minimizing the number of "overwrites" resulting from inserting or deleting a sequence of key values to/from the $B^+$-tree. However, in addition to this factor, the size of a physical page allocated to a node can affect the maintenance cost of the $B^+$-tree. In this paper, with diverse experiments, we compare and analyze the costs of construction and search of the $B^+$-tree and the space requirement on flash memory as the node size increases. We also provide sorting-based or non-sorting-based algorithms to be used when inserting a key value into the node and suggest an header structure of the index node for searching a given key inside it efficiently.

Folate nutrition is related to neuropsychological functions in the elderly

  • Chang, Nam-Soo;Kim, Eun-Jung;Kim, Ki-Nam;Kim, Hye-Sook;Kim, Seong-Yoon;Jeong, Bum-Seok
    • Nutrition Research and Practice
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    • v.3 no.1
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    • pp.43-48
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    • 2009
  • We investigated the nutritional state of B vitamins and the neuropsychological functions in 25 subjects, aged $63.1{\pm}6.3$ years, residing in rural areas of Korea. Nutritional states of thiamin, riboflavin, and pyridoxine were assessed enzymatically in the erythrocytes, and folate concentrations were measured microbiologically in the plasma and erythrocytes. A battery of composite neuropsychological test was administered to the subjects. Plasma folate was correlated with the total intelligence score (p=0.049). Folate levels in the erythrocytes were correlated with the performance intelligence scores such as block design (p=0.017) and picture arrangement (p=0.016). The red cell folate was correlated with memory scores such as general memory (p=0.009) and delayed recall (p=0.000). Although it did not reach statistical significance, verbal memory (p=0.053) was highly correlated with the red cell folate. The red cell folate was also correlated positively with the percent of conceptual level response number score (p=0.029), and negatively with the grooved pegboard test score for the non-dominant hand (p=0.010). Fine motor coordination was also influenced by folate nutrition, as finger tapping scores in both hands were significantly correlated with red cell folate (dominant hand; p=0.026, non-dominant hand; p=0.004). Other B vitamins such as thiamin, riboflavin, and vitamin $B_6$ were not as strongly correlated with neuropsychological function test scores as folate was. These results suggest that folate nutrition influences neuropsychological function test scores significantly in humans. Further studies are needed to explore the relationship between folate or other vitamin B nutrition and neuropsychological functions and the implications thereof.

A Design Method of a Completion Signal Generation Circuit of Memory for Asynchronous System (비동기식 시스템을 위한 메모리의 동작 완료 신호 생성 회로)

  • 서준영;이제훈;조경록
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.105-113
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    • 2004
  • This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

Design of a 64b Multi-Time Programmable Memory IP for PMICs (PMIC용 저면적 64비트 MTP IP 설계)

  • Cui, Dayong;Jin, Rijin;Ha, Pang-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.4
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    • pp.419-427
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    • 2016
  • In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.