• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.180-187
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• 2014

In this paper, a extension of a fixed-complexity sphere decoder (FSD) to perform interference signal detection and cancelling is proposed for downlink multiuser multiple input-multiple output (MIMO) communication system. It is based on the application of channel matrix expansion on generalized sphere decoder (GSD), and modification of the channel matrix ordering scheme to a FSD algorithm for interference detection. A Monte Carlo simulation shows that the proposed algorithm improves the receiver performance by 3 dB as compared to maximum likelihood detection without interference cancelling at 10% packet error rate in configuration of 702 Mbit/s datarate for four users respectively on IEEE802.11ac.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.261-265
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• 2008

This work presents a simplified efficient blind detection algorithm for orthogonal space-time codes(OSTBC). First, the proposed decoder exploits a proper decomposition approach of the upper triangular matrix R, which resulted from Cholesky-factorization of the composition channel matrix, to form an easy-to-solve blind detection equation. Secondly, in order to avoid suffering from the high computational load, the proposed decoder applies a sub-optimal QR-based decoder. Computer simulation results verify that the proposed decoder allows to significantly reduce computational complexity while still satisfying the bit-error-rate(BER) performance.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.257-262
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• 2016

A two-dimensional optical code division multiple access (OCDMA) en/decoder composed of four double-ring resonator add/drop filters and three delay waveguides is designed, and a transfer matrix method combined with fast Fourier transform is implemented to provide numerical simulations for the en/decoder. The auto-correlation peak level over the maximum cross-correlation level is larger than 3 at the center of the correctly decoded pulse for most of wavelength hopping and spectral phase code combinations, which assures the BER lower than 10^-3 which corresponds to the forward error correction limit.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2013-2014
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• 2006

For large capacity optical CDMA networks, we propose a shared-type encoder/decoder based on an tunable wavelength conveter (TWC) and an arrayed waveguide grating (AWG) router. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using three types of wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC), the generalized multi-wavelength Reed-Solomon code(GMWRSC) and the matrix code. Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.