• 대한기계학회논문집A
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• 제20권10호
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• pp.3135-3141
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• 1996

In order to develop an efficient algorithm for S-to-M mapping in CMCA, characteristics of CMCA mappings is studied and conceptual mapping procedure is physically described. Then, careful observations on the mapping procedure and experience reveal a simple algorithm of the S-to-M mapping. The algorithm is described and compared with other procedures for S-to-M mapping. It is found very efficient in terms of computational operations and processing time.

• 전자공학회논문지S
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• 제35S권5호
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• pp.48-58
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• 1998

In this paper, we proposed a new algorithm using characteristics of th ereconstructed phase trajectory by topological mapping developed for a real-tiem detection of the QRS complexes of ECG signals. Using fill-factor algorithm and mutual information algorithm which are in genral used to find out the chaotic characteristics of sampled signals, we inferred the proper mapping parameter, time delay, in ECG signals and investigated QRS detection rates with varying time delay in QRS complex detection. And we compared experimental time dealy with the theoretical one. As a result, it shows that the experimental time dealy which is proper in topological mapping from ECG signals is 20ms and theoretical time delays of fill-factor algorithm and mutual information algorithm are 20.+-.0.76ms and 28.+-.3.51ms, respectively. From these results, we could easily infer that the fill-factor algorithm in topological mapping from one-dimensional sampled ECG signals to two-dimensional vectors, is a useful algorithm for the detemination of the proper ECG signals to two-dimensional vectors, is a useful algorithm for the detemination of the proper time delay. Also with the proposed algorithm which is very simple and robust to low-frequency noise as like baseline wandering, we could detect QRS complex in real-time by simplifying preprocessing stages. For the evaluation, we implemented the proposed algorithm in C-language and applied the MIT/BIH arrhythmia database of 48 patients. The proposed algorithm provides a good performance, a 99.58% detection rate.

• ETRI Journal
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• 제36권6호
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• pp.913-923
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• 2014

This paper proposes a global mapping algorithm for multiple robots from an omnidirectional-vision simultaneous localization and mapping (SLAM) approach based on an object extraction method using Lucas-Kanade optical flow motion detection and images obtained through fisheye lenses mounted on robots. The multi-robot mapping algorithm draws a global map by using map data obtained from all of the individual robots. Global mapping takes a long time to process because it exchanges map data from individual robots while searching all areas. An omnidirectional image sensor has many advantages for object detection and mapping because it can measure all information around a robot simultaneously. The process calculations of the correction algorithm are improved over existing methods by correcting only the object's feature points. The proposed algorithm has two steps: first, a local map is created based on an omnidirectional-vision SLAM approach for individual robots. Second, a global map is generated by merging individual maps from multiple robots. The reliability of the proposed mapping algorithm is verified through a comparison of maps based on the proposed algorithm and real maps.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• 대한전자공학회논문지SD
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• 제39권8호
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• pp.84-91
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• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• Kyungpook Mathematical Journal
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• 제55권4호
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• pp.933-951
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• 2015

In this paper, we consider the problem of convergence of an iterative algorithm for a general system of variational inequalities, a nonexpansive mapping and an ${\eta}$-strictly pseudo-contractive mapping. Strong convergence theorems are established in the framework of real Banach spaces.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2003년도 Proceedings of ACRS 2003 ISRS
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• pp.1272-1274
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• 2003

In this paper, we present a new algorithm for high dimensional data reduction based on wavelet decomposition and Genetic Algorithm (GA). Comparative results show the superiority of our algorithm for dimensionality reduction and accuracy improvement.

• 대한수학회지
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• 제49권1호
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• pp.187-200
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• 2012

In this paper, we introduced a new extended extragradient iteration algorithm for finding a common element of the set of fixed points of a nonexpansive mapping and the set of solutions of equilibrium problems for a monotone and Lipschitz-type continuous mapping. And we show that the iterative sequences generated by this algorithm converge strongly to the common element in a real Hilbert space.