• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.125-130
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• 2009

This paper reviews the characteristics technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• Journal of IKEEE
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• v.12 no.3
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• pp.176-183
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• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.239-245
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• 2016

In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.7-14
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• 2012

A image quality is limited by a sample-and-hold circuit of the X-ray CMOS image sensor even though simple mos switch or bootstrapped clock circuit are used to get high quality sampled signal. Because distortion of sampled signal is produced by the charge injection from sample-and-hold circuit even using bootstrapped. This paper presents the 3D micro-inductor design methode in the CMOS process. Using this methode, it is possible to increase the ENOB (effective number of bit) through the use of micro-inductor which is calculated and designed in standard CMOS process in this paper. The ENOB is improved 0.7 bit from 17.64 bit to 18.34 bit without any circuit just by optimized inductor value resulting in verified simulation result. Because of this feature, micro-inductor methode suggested in this paper is able to adapt a mamography that is needed high resolution so that it help to decrease patients dose amount.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.15-21
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• 2011

In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.79-84
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• 2007

In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.47-51
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• 2013

A high power MOSFET switch based on a 0.35 ${\mu}m$ CMOS process has been developed for the protection IC of a rechargeable battery. In this process, a vertical double diffused MOS (VDMOS) using 3 ${\mu}m$-thick epi-taxy layer is integrated with a Zener diode. The p-n+Zener diode is fabricated on top of the VDMOS and used to protect the VDMOS from high voltage switching and electrostatic discharge voltage. A fully integrated digital circuit with power devices has also been developed for a rechargeable battery. The experiment indicates that both breakdown voltage and leakage current depend on the doping concentration of the Zener diode. The dependency of the breakdown voltage on doping concentration is in a trade-off relationship with that of the leakage current. The breakdown voltage is obtained to exceed 14 V and the leakage current is controlled under 0.5 ${\mu}A$. The proposed integrated module with the application of the power MOSFET indicates the high performance of the protection IC, where the overcharge delay time and detection voltage are controlled within 1.1 s and 4.2 V, respectively.