• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1575-1579
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• 1999

Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.101-104
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• 2004

음성속도변환(TSM : Time Scaling Modification) 알고리즘은 시간축에서 음성 신호의 속도를 변환할 수 있는 방식이다. 이러한, 방법으로는 OLA(Overlap Add), SOLA (Synchronized Overlap Add) 알고리즘 등이 연구 되어 왔다. 2 가지 방식 중에도 동기화를 시켜 overlap 을 시키는 SOLA 알고리즘이 OLA 방법에 비해 음질이 우수하다. 본 논문에서는 TMS320C5416 DSP 에 계산량이 감소된 SOLA 알고리즘을 실시간 구현하였다. 기존의 SOLA 알고리즘에서 동기화를 위해 사용하고 있는 cross-correlation 함수는 곱셈연산에서 발생하는 bit 의 dynamic range 가 커서 나눗셈 연산에서도 과도한 연산량을 필요로 한다. 따라서 이러한 계산량의 감소를 위해 기존의 cross-correlation 함수가 대신 더하기와 빼기의 연산으로 수행되는 NAMDF 함수를 사용하여 계산량을 줄였다. 제안한 방법을 SOLA 알고리즘에 적용하여 성능 평가를 실시하였다. TMS320C5416 DSP 에 실시간으로 실험한 결과 NAMDF 함수를 사용하였을 경우 음질의 저하가 거의 없었으며, 계산량을 기존의 cross-correlation 방식에 비해 6.22MIPS 가까이 감소시킬 수 있었다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.67-72
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• 2004

AC servo system has been implemented to FA system and also depends on its quality. Recently with the development of power switching device and DSP which has peripheral devices to control AC servo system, the servo technology has met a new development opportunity. A DSP based AC servo system with a 3-phase PMSM is proposed. The newly produced DSP TMX320F2812-version C which has the performance of fast speed, 150MIPS, and rich peripheral interface is used. Also space vector pulse width modulation (SVPWM) and the digital PI control are implemented to the servo system

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.13-24
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• 2003

Grid technology requires use of geographically distributed resources from multiple domains. Resource monitoring services or tools consisting sensors or agents will run on many systems to find static resource information (such as architecture vendor, OS name and version, MIPS rate, memory size, CPU capacity, disk size, and NIC information) and dynamic resource information (CPU usage, network usage(bandwidth, latency), memory usage, etc.). Thus monitoring itself may cause system overhead. This paper proposes the optimal monitoring interval to reduce the cost of monitoring services and the dynamic monitoring interval to measure monitoring events accurately. By employing two features, we find out unnecessary system overhead is significantly reduced and accuracy of events is still acquired.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.331-338
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• 2003

Cluster is the cost-effective parallel processing environment, and consists of the off-the-shelf computers connected by the computer net works. The characteristics of cluster are the node heterogeneity, the variety of node load, and the variety of network load. Because these characteristics influence the performance of parallel program executions, the load sharing for cluster is important, and by using the proper load sharing strategy, we can reduce the execution time of parallel programs. In this paper, we propose modified GSS algorithm, αGSS. In the proposed load sharing algorithms α GSS, the size of tasks are decided using the BogoMIPS of node. From the result of out experiments, we conclude that the proposed αGSS algorithm is effective in the heterogeneous cluster.

• Macromolecular Research
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• v.10 no.2
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• pp.122-126
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• 2002

A molecularly imprinted polymer (MIP) having both amidine and imidazole functional groups in the active site has been prepared using p-nitrophenyl phosphate as a transition state analogue (TSA). The imprinted polymer MIP with amidine and imidazole found to have the highest hydrolysis activity compared with other MIPs with either amidine or imidazole groups only. It is postulated a cooperative effect between amidine and imidazole in the hydrolysis of p-nitrophenyl methyl carbonate (NPMC) as a substrate when both groups were arranged in proximity by molecular imprinting. The rate enhancement of the hydrolysis by MIP was 60 folds over the uncatalyzed solution reaction and two folds compared with the control non-imprinted polymer CPI having both functional groups. The enzyme-mimetic catalytic hydrolysis of p-nitrophenyl acetate by MIP was evaluated in buffer at pH 7.0 with $K_{m}$ of 1.06 mM and $k_{cat}$ of 0.137 $h^{-1}$ . . .

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• The Bulletin of The Korean Astronomical Society
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• v.39 no.2
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• pp.53.2-53.2
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• 2014

Radial color gradient of early type galaxies (ETGs) is a key tool for studying the evolution of these galaxies. In this work, we investigated whether ETGs having negative or positive color gradients show any distinguishable characteristics in the galaxy properties. We selected sample of 211 ETGs at 0.01 < z < 0.5 in the Spitzer FLS field, then we constructed u-R color gradients. We obtained the stellar mass, specific star formation rate and fluxes of emission lines of each ETG from MPA-JHU DR7 catalog. Spitzer IRAC and MIPS 24 micron data were used to detect dust emission from the ETGs. Preliminary result shows that less massive galaxies are likely to have positive color gradients, which is probably due to the ongoing star formation in the galaxy core. Almost all AGNs have negative color gradients. This probably is because AGNs are located in relatively massive galaxies with little ongoing star formation. There exists a marginal difference in the percentage of galaxies with PAH emission between ETGs having positive color gradient and negative color gradient. This also supports that ETGs with positive color gradient are galaxies having enhanced star formation.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.1
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• pp.79.1-79.1
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• 2012

We present here $UBVI$ and H${\alpha}$ photometric results of stellar sources in the bubble nebula NGC 7635. The early type members are selected from the photometric membership criteria. H${\alpha}$ photometry allows us to detect 11 pre-main sequence candidates with H${\alpha}$emission. In addition, we performed PSF photometry for the Spitzer IRAC and MIPS 24${\mu}m$ images from archive (program ID 20726, PI: J. Hester) in order to search for the young stellar objects (YSOs). Total 19 sources are classified as YSOs (7 class I, 11 class II, and 1 transitional disk candidates) in the color-color diagrams according to the classification scheme of Gutermuth et al.. Among them, 7 YSOs have counterparts in optical photometric data. These stars can be divided into two groups at given color indices. It implies that there occurred the star formation events more than twice. We would like to discuss the star formation history in the bubble nebula using the results from SED fitter (Robitaille et al.), color composite image from IRAC bands, and spatial distribution of early type stars and YSOs.

• ETRI Journal
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• v.11 no.4
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• pp.105-118
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• 1989

HARP(High performance Architecture for RISC type Processor)는 고유의 명령어 세트, 데이터 타입, 메모리 입출력, 예외 처리 기능을갖는 32비트 VLSI 프로세서 구조이다. 마이크로 아키텍츄어는 설계된 구조를 기대할 수 있는최고 성능을 갖도록 구조(architecture)와 구현(implementation) 사이의 최적 모델링을 통해 정의되는 구조체로서 구조의 개념 설계를 구현의 실물 설계로 변환 시켜주는 조율(tuning)모델이다. HARP의 고유한 명령어 세트를 비롯한 구조적 기능들을 최적 구현 하기위해 32비트 크기의 명령어 입력 유니트(Instruction Fetch Unit), 데이터 입출력 유니트(Data I/O Unit), 명령어/데이터 처리유니트(Instruction/Data Processing Unit), 예외 상황 처리 유니트(Exception Processing Unit)등 4개 유니트가 설계되었으며 이들 4개 유니트의 동작을 최대 속도로 유지시키기 위해 각급 주요 설계 변수들이 시뮬레이션을 통해 최적화 되었다. 유효 채널길이 $0.7\mum$급 3층 메탈 배선의 HCMOS(High performance CMOS)공정 기술을 구현 기준 기술로 사용하여 50MHz외 동작 주파수에서 최대50 MIPS(Million Instructions Per Second)의 성능을 갖도록 3단계 파이프라인이 설계되었다. 단일 위상의 50MHz클럭 입력과 동기화된 명령어/데이터 입출력을 위해 액세스 타임 20nsec이내의 고속 메모리 입출력 구조가 시뮬레이션되었으며 설계된 마이크로 아키텍츄어를 이용하여 HARP구조의 기대된 최대 성능을 검증하였다.