• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.84-93
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• 2001

An electromagnetic micro x-y stage for probe-based data storage (PDS) has been fabricated. The x-y stage consists of a silicon body inside which planar copper coils are embedded, a glass substrate bonded to the silicon body, and eight permanent magnets. The dimensions of flexures and copper coils were determined to yield $100{\;}\mu\textrm{m}$ in x and y directions under 50 mA of supplied current and to have 440 Hz of natural frequency. For the application to PDS devices, electromagnetic stage should have flat top surface for the prevention of its interference with multi-probe array, and have coils with low resistance for low power consumption. In order to satisfy these design criteria, conducting planar copper coils have been electroplated within silicon trenches which have high aspect ratio ($5{\;}\mu\textrm{m}$in width and $30{\;}\mu\textrm{m}$in depth). Silicon flexures with a height of $250{\;}\mu\textrm{m}$ were fabricated by using inductively coupled plasma reactive ion etching (ICP-RIE). The characteristics of a fabricated electromagnetic stage were measured by using laser doppler vibrometer (LDV) and dynamic signal analyzer (DSA). The DC gain was $0.16{\;}\mu\textrm{m}/mA$ and the maximum displacement was $42{\;}\mu\textrm{m}$ at a current of 180 mA. The measured natural frequency of the lowest mode was 325 Hz. Compared with the designed values, the lower natural frequency and DC gain of the fabricated device are due to the reverse-tapered ICP-RIE process and the incomplete assembly of the upper-sided permanent magnets for LDV measurements.

• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.990-995
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• 2005

This paper reports the fabrication and characterization of $5\;\times\;5$ thermal cantilever array for nano-scaled memory device application. The $5\;\times\;5$ thermal cantilever array with integrated tip heater has been fabricated with MEMS technology on SOI wafer using 7 photo masking steps. All single-level cantilevers have a diode in order to eliminate any electrical cross-talk between adjacent tips. Electrical measurements of fabricated thermal cantilever away show its own thermal heating mechanism. Thermal heating is demonstrated by the reflow of coated photoresist on the cantilever array surface.

• 센서학회지
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• 제22권1호
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• 센서학회지
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• 제21권3호
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• pp.217-222
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• 2012

Optical coherence tomography(OCT) is a noninvasive optical imaging tool for biomedical applications. OCT can provide depth resolved two/three dimensional morphological images on biological samples. In this paper, we integrated an OCT system that was composed of an SLED(Superluminescent Light Emitting Diode, ${\lambda}_0$=1305 nm bandwith= 141 nm), a reference arm adopting a rapid scanning optical delay line(RSOD) to get high speed imaging, and a sample arm that used a micro electro mechanical systems(MEMS) scanning mirror. The sample arm contained a compact probe for imaging dental structures. The performance of the system was evaluated by imaging in-vivo human teeth with dental calculus, and the results indicated distinct appearance of dental calculus from enamel, gum or decayed teeth. The developed probe and system could successfully confirm the presence of dental calculus with a very high spatial resolution($6{\mu}m$).

• 인재니움
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• 제8권2호
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• pp.51-57
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• 2001

• 한국표면공학회지
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• 제47권6호
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• pp.362-367
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• 2014

We report the design, fabrication of a $Si_3N_4$ probe and calculation of its mechanical properties for DPN(dip pen nanolithography), which consists of dual tips. Concept of dual tip probe is to employ individual tips on probe as either an AFM tip for imaging or a writing tip for nano patterning. For this, the dual tip probe is fabricated using low residual stress $Si_3N_4$ material with LPCVD deposition and MEMS fabrication process. On the basis of FEM analysis we show that the functionality of dual tip probe for imaging is dependent on the dimensions of dual tip probe, and high ratio of widths of beam areas is preferred to minimize curvature variation on probe.

• 한국전자파학회논문지
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• 제23권2호
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• pp.177-186
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• 2012

본 논문에서는 프로브 커넥터 핀의 누화 특성이 -30 dB 이하를 만족시키는 핀의 피치 및 길이 파라미터에 대한 설계 기준을 제시하였다. 프로브 커넥터 핀의 누화 특성을 분석하기 위하여 격자 구조로 배열된 프로브커넥터 핀의 인덕턴스 성분과 커패시턴스 성분을 추출하였으며, 접지 핀의 개수가 증가해도 이미 계산된 파라미터들을 이용해서 새로운 커패시턴스 및 인덕턴스 성분들을 쉽게 계산할 수 있음을 보였다. 또한, 신호(signal)핀 주변에 위치한 접지(ground) 핀 개수를 증가시키면서 누화 특성을 향상시키는 알고리즘을 제시하였으며, 특히 접지 핀 개수의 증가가 자기장 결합(inductive coupling)에 의한 누화를 효과적으로 제거시킨다는 것을 보였다. 최종적으로는 주어진 접지 핀 개수 및 형상 하에서 -30 dB 이하의 누화 특성을 만족하는 핀의 피치 및 길이를 결정하는 영역을 도시하였으며, 이는 프로브 커넥터 시스템의 누화 특성 설계 시 유용하게 사용할 수 있을 것으로 사료된다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 춘계학술대회 논문요약집
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• pp.156-156
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• 2004

정보화 및 휴대화 시대에 있어서 폭증하는 정보량을 보다 작은 용기에, 보다 많이 그리고 보다 저렴하게 저장하기 위해서는, 기존 저장기기의 한계를 극복할 수 있는 새로운 개념의 차세대 정보 저장기기가 요구되어 진다. 나노미터 사이즈의 주사탐침이 기록매체표면에 근접하여 정보를 기록/재생하는 PSD는 상기한 저장기기의 대용량화, 소형화, 그리고 저가격화를 충족시킬 수 있는 신개념의 저장기기로, 그 기술적 근간을 SPM(Scanning Probe Microscope)기술과 MEMS(Micro Electro Mechanical Systems) 제작기술에 두고 있다.(중략)

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.240-240
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• 2009