• Journal of IKEEE
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• v.15 no.2
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• pp.171-178
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• 2011

In this paper, a novel pulse repetition interval (PRI) jittering coder based on quasi-random M-sequence codes is proposed for improvement of counter-countermeasure capability in a radar. Each of the proposed jittered 256 PRI codes has a unique code chip combination with 256 code chips, such that any set of three consequent code chips (4 pulses) from any code appears only once among the entire code chip sequences of the codes. This indicates that only 4 of received pulses are enough to determine uniquely the exact timing position of the incoming pulse train (or code chip sequence) required for counter-countermeasure, as well as the identity of the transmitted code. To prove the proposed idea experimentally, the jittered PRI coder is implemented and demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.22-29
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• 2012

By using the cyclic properties of symmetric balance incomplete block design(BIBD) codes and arrayed-waveguide grating(AWG) routers, a compact optical CDMA network coder-decoder(codec) can be constructed. It can be observed that the various code families obtained by BIBD improve the BER performance compared to M-sequence code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.829-835
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• 2002

When finite length image signal is decomposed into M-band synthesized using M-band orthogonal wavelet transform, the boundary signal of image are not reconstructed perfectly. for boundary signals to be reconstructed perfectly, different type filter bank or technique is applied to them when the dimension of analysed is proposed. It can be designed using the singular value decomposition of boundary perfect reconstruction matrix which is obtained from paraunitary matrix which is obtained from paraunitary matrix. And it is also discussed to design the boundary filter bank for improving the coding performance when it is applied to subband coder. The proposed boundary filter bank shows 7% gains in PSNR compared with reflected method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.91-97
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• 2004

A digital over-sampling noise-shaping coder to achieve the processing accuracy for the audio signal bandwidth is designed. In order to implement an optimized design of the noise-shaping coder as a form of U (intellectual property), circuit design techniques that optimize the multiplication and the ROM architectures are proposed with emphasis on the low-voltage operation under 2.0 V and the minimization of the hardware resources. In the design and verification methodology, the overall architectures and the internal bit width have been determined through behavioral simulations. The overall performances including timing margin have been estimated through transistor-level simulations. Furthermore, the test results of the implemented chip using a 0.35-${\mu}{\textrm}{m}$ standard CMOS process proposed the validity of the proposed circuits and the design methodology.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.914-918
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• 2000

In this paper, a next generation high speed QPSK transmitter is designed based on 1.8${\mu}$m design rule. The designed transmitter supports the MPEG2-TS coded packed data for the DAVIC standard. Transmitter is composed of the convolutional coder, the shortened Reed-Solomon coder, and QPSK modulator. The coded packets are modulated in APSK with an RC filter. Especially, Galois Field multiplier with a standard basis is designed with the pipelined parallel architecture. Also, in the QPSK modulator, the RC filter and mixer are simplified into the ROM table, which can improve the performance of the transmitter. The total number of gates for the implemented baseband transmitter is 26,875.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.297-300
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• 2007

Due to its impressive compression performance, the H.264 video coder is highlighted in the video communications industry, such as DMB (Digital Multimedia Broadcasting), PMP (Portable Multimedia Player), etc. The main bottleneck to use the H.264 coder lays in the computational complexity, i.e. five times more complex than the market leading MPEG-4 Simple Profile codec. In this paper, we propose the hierarchical mode decision method for intraframe coding for the reduction of the computation complexity of the encoder. By determining the mode group early, the propose algorithm can skip the computationally demanding computation in the mode decision. The proposed algorithm is composed of three steps: $16{\times}16$ mode decision, $4{\times}4$ mode-group decisions, and final mode decision among the selected mode group. The simulation results show that the proposed algorithm achieves 20% to 50% reduction in the computational complexity compared with the conventional algorithm.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.4
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• pp.97-103
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• 2001

The study on the high-speed machine tool is very important for the improvement of productivity since it can shortens cutting and non-cutting time. Especially, high speed of feed drive system is the major research field. In the industries of the advanced countries, the feed drive systems at the speed of 60 m/min have been already developed based on the high lead ball screws. In this study, a high speed feed drive system at the speed of 60 m/ min has been developed, and its movements characteris-tics are investigated. As the movement characteristics, positioning accuracy, angular accuracy, straightness and micro step-response are measured. Thermal characteristics of the system is also discussed. For measuring the movement characteris-tics, a laser interferometer, a memory-based Hi-coder and a cooling device are used. The experimental results confirm that the movement characteristics and the thermal behavior of the system are satisfactory in the aspect of accuracy and stability.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.167-168
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• 2000

We propose a signaling circuit that can reduce power consumption and Electromagnetic Interference (EMI) in a Liquid Crystal Display (LCD) controller-to-source driver interface. The proposed signaling circuit consists of a coder/decoder that can minimize temporal bit transitions in a transmission line and a current-mode driver that can convert voltage swing into a very small amount of current. We have simulated the proposed signaling circuit using the HSPICE and the proposed signaling circuit has been designed in a 0.25 ${\mu}m$ CMOS technology.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.383-385
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• 2007

웨이블릿 화상 코딩 기법은 자연적으로 레이어드된 비트스트림을 생성해 내기 때문에, 주파수 제한적인 채널 상황에서 에러에 강한 성능을 나타내고 있다. 본 논문에서는 Progressive Image Coder의 성능을 비교하고 평가하는 새로운 기법인 시각적 엔트로피를 이용해, 웨이블릿 영역에서 시각적인 가중치를 이용해 정량화하려고 한다. 이 시각적인 가중치는 주파수 영역과 공간 영역에서, 인간의 시각 체계(HVS, human visual system)에 기반 하여 만들어진 것으로, 웨이블릿 계수들의 코딩 순서를 결정하는 기준으로 사용되고, 이렇게 해서 시각적인 화질을 개선할 수가 있다. 정규화된 채널 용량이 0.3일 때, 전송 이득은 시각적 엔트로피로 측정해 보았을 때 23% 이상 얻을 수 있다.