• Transactions of the Korean Society of Mechanical Engineers
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• v.10 no.1
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• pp.34-42
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• 1986

An interface of a circular arc formed by two isotropic, homogeneous elastic materials is investigated. It is shown that L integral satisfies the conservation law for the interface if it is perfectly bonded, in frictionless contact or separated such as in a crack with the origin of the coordinate system being located at the center of the circular arc. The property of path independence of the L integral is applied to an interfacial crack problem, to obtain the stress intensity factors, where the interfacial crack is located along the arc of the circular inclusion embedded in infinite matrix. It is assumed here that the contact zone exist as in the model proposed by Comninou, thus removing the overlapping of the materials along the interface. Another example is shown for case of a circular interfacial crack in the matrix of finite size, where the stress intensity factors are determined by computing a value of the L integral numerically along the path far from the crack tip.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.30-38
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• 1998

In this paper, a new CMOS current-mode integrator is proposed that can apply the basic building block of the low-voltage high frequency current-mode active filter. And tuning circuits that control the gain and unity gain frequency of them is designed. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined transconductance and MOSFET gate capacitance can be expanded by the proposed integrator. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time integrator with NMOS-gm. And also, cut-off frequency and gain of the active filter can be controlled with the designed tuning circuit. From the result, we can reduce errors on fabrication. And then, 3rd-order low-pass active filter is designed as an application circuits. These results are verified by the small signal analysis and the 0.8$\mu\textrm{m}$ parameter HSPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.92-98
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• 2001

When analyzing the scatting problem of multi-layered planar structures using closed-form Green's function, one of the main difficulties is that the numerical integrations for the evaluation of diagonal matrix elements converge slowly and are not so stable. Accordingly, even when the integration fur the singularity of type $e^{-jkr}/{\gamma}$, corresponding to the source dipole itself, is performed using such a method, this difficulty persists in the integration corresponding to the finite number of complex images. In order to resolve this difficulty, a new technique based upon the Gaussian quadrature in polar coordinates for the evaluation of the two-dimensional generalized exponential integral is presented. Stability of the algorithm and convergence is discussed. Performance is demonstrated for the example of a microstrip patch antenna.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.605-608
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• 2010

두 영상에서 특징점을 추적하기 위하여 특징점을 중심으로 $N{\times}N$ 크기 윈도우 패치의 SSD 값을 비교하는 방법을 사용한다. 그러나 영상에서 다수의 특징점이 추출되어 매칭을 시도하는 경우 많은 처리 시간을 필요로 한다. 처리 시간의 증가는 실시간 처리를 어렵게 만든다. 이러한 문제를 해결하기 위하여 적분 영상(integral image)을 사용하여 매칭 가능성이 높은 특징점을 필터링하여 SSD 매칭의 처리 시간을 단축시키는 방법을 제안한다. 본 논문에서 제안한 적분 영상을 사용한 특징점 필터링을 적용한 방법과 기존의 SSD 매칭 방법을 비교 실험하여 특징점 매칭의 처리 시간을 절감하는 결과를 얻을 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3638-3644
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• 2009

A CMOS multi-channel low-voltage current mode filter circuit is designed. The designed current-mode filter is based on linear cascode current-mode integrator that is newly proposed in this paper. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain and unity gain frequency. The designed filter is composed with 5th Chebyshev function and converted to active version by signal flow graph method. We verified that the designed filter can be applied to three-channel basedband, bluetooth, DECT and WCDMA with 0.51MHz~7.03MHz frequency tuning range by Hspice simulation using 1.8V-$0.18{\mu}m$ CMOS technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4745-4750
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• 2012

In this paper a $6^{th}$ 1MHz~30MHz bandpass filter for Power line communication(PLC) modem receiver is designed using current mode synthesis method which is good to design the low-voltage and low-power filter. The designed bandpass filter is composed of cascade connecting between $3^{rd}$ Butterworth highpass filter and $3^{rd}$ Chebychev lowpass filter. As a core circuit in the current-mode filter, a current-mode integrator is designed with new architecture which can improve gain and unity gain frequency of the integrator. The gain and the unity gain frequency of the designed integrator is each 32.2dB and 247MHz. And the cutoff frequency of the designed $6^{th}$ bandpass filter can be controlled to 50MHz from 200KHz according to controlling voltage and the power consumption is 2.85mW with supply voltage, 1.8V. The designed bandpass filter was verified using a $0.18{\mu}m$ CMOS parameter.

• Journal of Advanced Marine Engineering and Technology
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• v.24 no.6
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• pp.24-33
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• 2000

This paper investigates the relationship between J-integral and crack tip opening displacement, ${\delta}_t$ using Gordens results of numerical analysis. Estimation were carried out for several strength levels such as ultimate, flow, yield, ultimate-flow, flow-yield stress to determine the influence of strain hardening and the ratio of crack length to width on the $J-{\delta}_t$ relationship. It was found that for SE(B) specimens, the $J-{\delta}_t$ relationship can be applied to relate J to ${\delta}_t$ as follows $J=m_j{\times}{\sigma}_i{\times}{\delta}_t$ where $m_j=1.27773+0.8307({\alpha}/W)$, ${\sigma}_i:{\sigma}_U$, ${\sigma}_{U-F}={\frac{1}{2}} ({\sigma}_U+{\sigma}_F$), ${\sigma}_F$, ${\sigma}_F}$ $Y=({\sigma}_F+{\sigma}_Y)$, ${\sigma}_Y$

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.8
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• pp.2158-2166
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• 1994

In order to understand the package crack emanating from the edge of leadframe after the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the M-integral and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the package crack are investigated taking into account the temperature dependence of the material properties, which simulates a more realistic condition. If the temperature dependence of the material properties is considered the result of analysis conforms with observations that the crack is kinked at between 50 and 65 degree. However, in case of constant material properties at the room temperature it is found that the J-integral is underestimated and the kink crack angle is different form the observation. The effects of the material properties and molding process temperature on J-integral and crack angle are less significant that the chip size for the cases considered here. It is suggested that the geometric factors such as ship size, leadframe size are to be well designed in order to prevent(or control) the occurrence and propagation of the package crack.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.36-43
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• 2015

A pixel-level readout circuit is studied for 2-dimensional microbolometer focal plane arrays (FPAs). A current mirroring injection (CMI) input circuit with 2-step current-mode bias suppression is proposed for a pixel-level architecture with high responsivity and long integration time. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a $320{\times}240$ microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed 2-step bias-current suppression has sufficiently low calibration error with wide calibration range, and the calibration range and error can be easily optimized by controlling some design parameters. Due to high responsivity and a long integration time of more than 1 ms, the noise equivalent temperature difference (NETD) of the proposed circuit can be improved to 26 mK, which is much better than that of the conventional circuits, 67 mK.