• Journal of the Korea Society of Computer and Information
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• v.28 no.12
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• pp.231-238
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• 2023

For boost PFC (Power Factor Correction) converters, various control methods are being studied to achieve unity power factor and low THD (Total Harmonic Distortion) of AC input current. Among them, average current mode control, which controls the average value of the inductor current to follow the current reference, is the most widely used. However, nowadays, as advanced digital control becomes possible with the development of digital processors, predictive control of boost PFC converters is receiving attention. Predictive control is classified into predictive current mode control, which generates duty in advance using a predictive algorithm, and model predictive current control, which performs switching operations by selecting a cost function based on a model. Therefore, this paper simply explains the average current mode control, predictive current mode control, and model predictive current control of the boost PFC converter. In addition, current control under entire load and disturbance conditions is compared and analyzed through simulation.

• KIISE Transactions on Computing Practices
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• v.22 no.7
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• pp.303-309
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• 2016

Recently, an increasing number of embedded processors such as ARM Mali begin to support GPGPU programming frameworks, such as OpenCL. Thus, GPGPU technologies that have been used in PC and server environments are beginning to be applied to the embedded systems. However, many embedded systems have different architectural characteristics compare to traditional PCs and low-power consumption and real-time performance are also important performance metrics in these systems. In this paper, we implement a parallel AES cryptographic algorithm for a modern embedded GPU using OpenCL, a standard parallel computing framework, and compare performance against various baselines. Experimental results show that the parallel GPU AES implementation can reduce the response time by about 1/150 and the energy consumption by approximately 1/290 compare to OpenMP implementation when 1000KB input data is applied. Furthermore, an additional 100 % performance improvement of the parallel AES algorithm was achieved by exploiting the characteristics of embedded GPUs such as removing copying data between GPU and host memory. Our results also demonstrate that higher performance improvement can be achieved with larger size of input data.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.47-54
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for imbedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro)-TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter-TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.117-124
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• 2007

In this paper we present a translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, each with an associated block buffer and a corresponding comparator. Either the block buffer or the main bank is selectively accessed on the basis of two bits in the block buffer (tag buffer). Dynamic power savings are achieved by reducing the number of entries accessed in parallel, as a result of using the tag buffer as a filtering mechanism. The performance overhead of the proposed TLB is negligible compared with other hierarchical TLB structures. For example, the two-cycle overhead of the proposed TLB is only about 1%, as compared with 5% overhead for a filter (micro) TLB and 14% overhead for a same structure without continuos accessing distinction algorithm. We show that the average hit ratios of the block buffers and the main banks of the proposed TLB are 95% and 5% respectively. Dynamic power is reduced by about 95% with respect to with a fully associative TLB, 90% with respect to a filter TLB, and 40% relative to a same structure without continuos accessing distinction algorithm.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.7
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• pp.569-573
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• 2016

Strengthened regulations for atmospheric emissions from ships have created a need for new and alternative power systems that offer low emissions and high energy efficiency. Recently, new types of propulsion power systems, such as fuel cell systems that use hydrogen as an energy source, have gained serious consideration in applications requiring emission control. The purpose of this work is to certify the availability of solid oxide fuel cell (SOFC) systems equipped with recycled steam reforming fuel processors, and to compare their performance with that of extra steam reforming systems. The results demonstrate that the recycled steam reforming system has a slightly lower cell voltage and higher energy efficiency than the extra steam reforming system.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.3
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• pp.323-332
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• 2014

Stepper motor is widely used in positioning applications due to its durability and high torque to inertia ratio as well as low cost and ability to be easily controlled with open-loop. Due to increased resolution of position control and improved stability of motion control, microstepping has drawn attention in industry since it was introduced in 1970s. With the increase in computational power and decrease in cost of embedded processors in recent years, drives and control systems for stepper motors have become more sophisticate than ever. Thus, closed-loop control methods have been developed to improve the performance of the stepper motors. In this paper, we review not only basic principles of conventional control methods used for stepper motors but also that of microstepping control. In addition, we surveyed recent development in nonlinear control methods applied to stepper motors. The nonlinear control methods are presented in the view of Lyapunov stability. Nonlinear torque disturbance observer, sliding mode control, and nonlinear phase compensation are also presented.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.815-824
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• 2013

Traditionally embedded microprocessors is considered as a device for low- and simple-computations because of its limited computing power and constrained resources. However high-end embedded devices have been developed and many applications are getting feasible in the embedded devices. To provide secure and robust service environments, security on embedded devices are in order. Recently many research results on embedded devices have been proposed. In this paper, we explore various cryptography implementation results on representative 8-, 16- and 32-bit embedded processors including AVR, MSP and ARM. This report would be helpful for following researchers who are interested in cryptography implementation techniques on resource constrained devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.153-156
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• 2009

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability ($0.22^{\circ}/hr$) and scale factor stability, extremely low angle random walk ($0.07^{\circ}/\sqrt{hr}$) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The CIC type of decimation block only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.