• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.6
• /
• pp.18-26
• /
• 2011

Debates concerning the competitive edge of leading 3DTV technology of the shutter glasses (SG) 3D and the film-type patterned retarder (FPR) are flaring up. Although SG technology enables Full-HD 3D vision, it requires complex systems including the sync transmitter (emitter), the sync processor chip, and the LCD lens in the active shutter glasses. In addition, the transferred sync-signal is easily affected by the external noise and a 3DTV viewer may feel flicker-effect caused by cross-talk of the left and right image. The operating current of the sync processor in the 3DTV active shutter glasses is gradually increasing to compensate the sync reconstruction error. The proposed chip is a low-power hardware sync processor based discrete-event SoC(system on a chip) designed specifically for the 3DTV active shutter glasses. This processor implements the newly designed power-saving techniques targeted for low-power operation in a noisy environment between 3DTV and the active shutter glasses. This design includes a hardware pre-processor based on a universal edge tracer and provides a perfect sync reconstruction based on a floating-point timer to advance the prior commercial 3DTV shutter glasses in terms of their power consumption. These two techniques enable an accurate sync reconstruction in the slow clock frequency of the synchronization timer and reduce the power consumption to less than about a maximum of 20% compared with other major commercial processors. This article describes the system's architecture and the details of the proposed techniques, also identifying the key concepts and functions.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.6
• /
• pp.2648-2668
• /
• 2016

Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.13 no.8
• /
• pp.3821-3841
• /
• 2019

Cloud radio access networks (C-RANs) have been regarded in recent times as a promising concept in future 5G technologies where all DSP processors are moved into a central base band unit (BBU) pool in the cloud, and distributed remote radio heads (RRHs) compress and forward received radio signals from mobile users to the BBUs through radio links. In such dynamic environment, automatic decision-making approaches, such as artificial intelligence based deep reinforcement learning (DRL), become imperative in designing new solutions. In this paper, we propose a generic framework of autonomous cell activation and customized physical resource allocation schemes for energy consumption and QoS optimization in wireless networks. We formulate the problem as fractional power control with bandwidth adaptation and full power control and bandwidth allocation models and set up a Q-learning model to satisfy the QoS requirements of users and to achieve low energy consumption with the minimum number of active RRHs under varying traffic demand and network densities. Extensive simulations are conducted to show the effectiveness of our proposed solution compared to existing schemes.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.17 no.6
• /
• pp.375-382
• /
• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.27 no.4
• /
• pp.33-44
• /
• 2023

Wind power is one of the most efficient and reliable energy sources in the transition to a low-carbon society. In particular, offshore wind power provides a high-quality and stable wind resource compared to onshore wind power while both present a higher installed capacity than other renewables. In this paper, we present our new program, the X-WIND program well suitable for the assessment of the substructure of offshore wind turbines. We have developed this program to increase the usability of analysis programs for offshore wind energy substructures by addressing the shortcomings of existing programs. Unlike the existing programs which cannot solely perform the substructure analyses or lack pre-post processors, our X-WIND program can complete the assessment analysis for the offshore wind turbines alone. The X-WIND program is embedded in AutoCAD so that both design and analysis are performed on a single platform. This also performs static and dynamic analysis for wind, wave, and current loads, essential for offshore wind power structures, and includes pre/post processors for designs, mesh developments, graph plotting, and code checking. With this expertise, our program enhances the usability of analysis programs for offshore wind energy substructures, promoting convenience and efficiency.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.19 no.6
• /
• pp.183-189
• /
• 2019

Despite its low cost, ARM is widely used in smartphones, digital cameras, home network devices, and wireless technologies because of its low power consumption and reliable performance. The domestic memory semiconductor design technology is in the world's highest level, but that of the processor is far less than that, which results in the technology unbalance between the memory and the processor. When designing a processor, exception and interrupt capabilities are requisite, but this is often omitted in the research stage. However, exception processing and interrupts must be included in order for the processor to function fully. In this paper, we design a 32-bit ARMv4 family of processors with exception handling and interrupts using VHDL and verify with ModelSim. As a result, ARM's exception and interrupts are successfully performed.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.6
• /
• pp.33-39
• /
• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.5
• /
• pp.43-51
• /
• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.8
• /
• pp.1-10
• /
• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.5
• /
• pp.252-259
• /
• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).