• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.27-34
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• 2009

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.159-166
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• 2010

For a grid-connected inverter in distributed generation systems, the current control is essential, and recently, the predictive current control based on a high performance digital signal processors (DSP) to satisfy a fast dynamic response has been widely investigated. However, the performance of predictive current control is degraded by the time delay due to digital implementation, the parameter and measured value errors and the interference of noise, and also theses make system even unstable. Therefore, this paper proposes the predictive current control using grid voltage observer for grid-connected inverter applications. To determine the relevant voltage observer gain, the low-order harmonics of grid voltage are considered, and the effect of filter parameter errors is analyzed. The proposed method has a fast current response capability, the robustness to noise and simple implementation due to voltage sensorless control and the robust current control performance to low-order grid harmonics. The feasibility of the proposed method is verified by simulation and experimental results.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.554-558
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• 2004

In this paper, we introduce noise prediction program of HVAC system to assist low-noisy design of ship's cabin. The developed program calculates sound power levels at HVAC components considering primary and secondary noise generated by fan and duct element, duct element noise attenuation, and duct break-in noise based on the authentic empirical method suggested by NEBB and acoustic power balancing method. Sound pressure level at cabin with or without ceiling system is evaluated by the diffuse-field theory considering diffuser and duct break-out sound powers. Moreover, the program provides intuitive pre- and post-processors using modem GUI functions to help efficient modeling and evaluation of cabin and HVAC component noise. To validate the accuracy and convenience of the program, noise prediction for a HVAC system is demonstrated.

• ETRI Journal
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• v.44 no.3
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• pp.379-388
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• 2022

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.466-474
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• 2014

According to wireless network technology and mobile processors performance were improved, the small wireless mobile device such as smart phones has been widely utilized. The mobile devices can be used GPS information, thereby the services based on location information was increased. GPS was impossible to provide location information in indoor and signal shading environment, and the tracking systems based on short distance wireless communication are required infrastructure. The IEEE 802.11 based tracking system is possible estimation using APs, however the tracking device is exhausted battery power seriously. In this paper, we propose IEEE 802.11 based low-power tracking system. We reduced power consumption from channel scanning and network connection. For performance evaluation, we designed and implemented the tracking tag device, and measured power consumption of the device. As the simulation result, we confirmed that the power consumption was reduced 46% compare to the standard execution.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.530-540
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• 2001

As mobile applications are required to handle more computing-intensive tasks, many mobile devices are designed using VLIW processors for high performance. In VLIW machines where a single instruction contains multiple operations, the power consumption during instruction fetches varies significantly depending on how the operations are arranged within the instruction. In this paper, we describe a post-pass optimal operation rearrangement method for low-power VLIW instruction fetch, The proposed method modifies operation placement orders within VLIW instructions so that the switching activity between successive instruction fetches is minimized. Our experiment shows that the switching activity can be 34% on average fro benchmark programs.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.269-274
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• 2008

Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.