• 대한전자공학회논문지SD
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• 제48권10호
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• pp.33-38
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• 2011

본 논문에서는 로컬에서의 동기화를 위한 새로운 저 전력 동기화 기술을 제안하였다. 본 논문에서 제안하고 있는 저 전력 동기화 기술은 현재 널리 이용되고 있는 소스 동기화 방법과 비교하여 클록을 전송하는 대신 인에이블 신호를 전송하여 동기화를 함으로써 소스 동기화 방법의 장점과 데이터 전송속도는 그대로 유지하면서 동기화를 위한 회로와 배선에서 소모되는 전력을 50%이상 감소시킨다.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• Journal of Power Electronics
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• 제16권1호
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• pp.340-350
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• 2016

A cascaded hybrid multilevel inverter including a reconfiguration technique for low voltage dc distribution applications is proposed in this paper. A PWM generation fault detection and reconfiguration paradigm after an inverter cell fault are developed by using only a single-chip controller. The proposed PWM technique is also modified to reduce switching losses. In addition, the proposed topology can reduce the number of required power switches compared to the conventional cascaded multilevel inverter. The proposed technique is validated by using a 3-kVA prototype. The switching losses of the proposed multilevel inverter are also investigated. The experimental results show that the proposed hybrid inverter can improve system efficiency, reliability and cost effectiveness. The efficiency of proposed system is 97.45% under the tested conditions. The proposed hybrid inverter topology is a promising method for low voltage dc distribution and can be applied for the multiple loads which are required in a data center or telecommunication building.

• 대한임베디드공학회논문지
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• 제8권4호
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• pp.195-204
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• 2013

The embedded software has been developed in the forms of various versions that provides similar service based on product family. For increase usefulness of product family, software must has well-structured and reusable properties. Software architecture is important to improve adaptability in model-based development of embedded software mounted onto product family. In this paper, we proposed a technique of ADD(Attribute-Driven Design)-based software architecture design for low power software development. This technique provides a chance to consider the power consumption issue in design phase of software, and makes possible to develop low power embedded software.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.5-6
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• 2012

In this paper, a simplified maximum power point tracking technique for the solar charger is presented. Main advantages of the proposed charger include low cost and optimized charge time. The maximum power point tracking method is used to deliver the maximum power from PV array to the battery thereby reducing the charge time. Moreover, the proposed technique which tracks the maximum power point by adjusting output current helps reduce the quantity of required number of sensors for the charger. The experimental protype was implemented by using an 80W PV array, a buck converter and a digital signal processor to verify the feasibility of the proposed method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.425-430
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• 1998

This paper presents a high performance low switching PWM technique for the propulsion system of railway such as subway and high speed train. In order to achieve the continuous voltage control to six-step and a low harmonics with low switching frequency under 500Hz, the synchronous PWM technique is combined with a space vector overmodulation and implemented by using DSP. Improved performance and a validation of proposed method are showed by the digital simulation and the experimental results using a 1.65MVA IGBT VVVF inverter and inertia load equivalent to 160 tons railway vehicles.

• 센서학회지
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• 제27권1호
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• pp.31-35
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• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.