Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Low-Power Synchronization Technique for On-Chip Communication

온 칩 통신을 위한 저 전력 동기화 기술

  • Lee, Jung-Hyun (Department of Electrical and Computer Engineering, Hanyang University) ;
  • Kim, Dong-Chul (Department of Electrical and Computer Engineering, Hanyang University) ;
  • Eo, Yung-Seon (Department of Electrical and Computer Engineering, Hanyang University)
  • 이정현 (한양대학교 통신공학과) ;
  • 김동철 (한양대학교 통신공학과) ;
  • 어영선 (한양대학교 통신공학과)
  • Received : 2011.06.30
  • Accepted : 2011.10.10
  • Published : 2011.10.25
Download PDF
⟨ Previous Next ⟩

Abstract

A novel low-power synchronization technique is presented for the local synchronization. Since the proposed technique transmits an enable signal instead of a clock signal which consumes large power, it can considerably reduce the power consumption. The source-synchronization scheme which is widely adopted for the local synchronization is compared with the proposed technique. It is shown that the proposed low-power synchronization technique provides approximately 50% power saving.

본 논문에서는 로컬에서의 동기화를 위한 새로운 저 전력 동기화 기술을 제안하였다. 본 논문에서 제안하고 있는 저 전력 동기화 기술은 현재 널리 이용되고 있는 소스 동기화 방법과 비교하여 클록을 전송하는 대신 인에이블 신호를 전송하여 동기화를 함으로써 소스 동기화 방법의 장점과 데이터 전송속도는 그대로 유지하면서 동기화를 위한 회로와 배선에서 소모되는 전력을 50%이상 감소시킨다.

Keywords

References

  1. K. Lee, S. Lee, and H. Yoo, "Low-power networks-on-chip for high-performance SoC design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 2, pp. 148-160, Feb. 2006.
  2. M. Ghoneima, Y. Ismail, M. Khellah, and V. De,"SSMCB : Low-power variation-tolerant source-synchronous multicycle bus," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 2, pp. 384-394, Feb. 2009. https://doi.org/10.1109/TCSI.2008.2001805
  3. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "Low-power, high-speed transceivers for network-on- chip communication," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no.1, pp. 12-21, Jan. 2009. https://doi.org/10.1109/TVLSI.2008.2001949
  4. K. Lee, S. Lee, and H. Yoo, "A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform," in Proc. ISSCC, pp. 152-518, San Francisco, CA, Feb. 2004.
  5. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Theory of latency -insensitive design," IEEE Trans. Comput.- Aided Des. Integr. Syst., vol. 20, no. 9, pp. 1059-1076, Sep. 2001. https://doi.org/10.1109/43.945302
  6. L. Scheffer, "Methodologies and tools for pipelined on-chip interconnect," in Proc. IEEE ICCD, pp. 152-157, Freiburg, Germany, Sep. 2002.
  7. R. Lu, G. Zhong, C.-K. Koh, and K.-Y. Chao, "Flip-flop and repeater insertion for early interconnect planning," in Proc. DATE, pp. 690 -695. Paris, France, Mar. 2002.
  8. P. Cocchini, "Concurrent flip-flop and repeater insertion for high performance integrated circuits," in Proc. ICCAD, pp. 268-273, San jose, CA, Nov. 2002.
  9. M. Ghoneima and Y. Ismail, "Optimum positioning of interleaved repeaters in bidirectio₋ nal buses," IEEE Trans. Comput.-Aided Des. Integr. Syst., vol. 24, no. 3, pp. 461-469, Mar. 2005. https://doi.org/10.1109/TCAD.2004.842801