• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• ETRI Journal
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• v.25 no.5
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1037-1043
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• 2020

This paper presents a new Physical Unclonable Function (PUF) security chip based on a low-cost, small-area, and low-power semiconductor process for IoT devices. The proposed security circuit has multiple challenge-to-response pairs (CRP) by adding the switching circuit to the cross-coupled path between two inverters of the SRAM structure and applying the challenge input. As a result, the proposed structure has multiple CRPs while maintaining the advantages of fast operating speed and small area per bit of the conventional SRAM based PUF security chip. In order to verify the performance, the proposed switched SRAM based PUF security chip with a core area of 0.095㎟ was implemented in a 180nm CMOS process. The measurement results of the implemented PUF show 4096-bit number of CRPs, intra-chip Hamming Distance (HD) of 0, and inter-chip HD of 0.4052.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.69-72
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• 2000

This paper describes an SRAM write driver circuit which dissipates small power. The write driver utilizes a dual sized transistor structure to reduce operating current in the write cycle. In the case of higher voltage comparing to Vcc, only one transistor is active, while in the case of low Vcc two transistors are active so as to deliver the current twice. Thus though with the high voltage operation, the power consumption is reduced with keeping the speed in a given specification. Simulation results have verified the functionality of the new circuit and write power is reduced by 7 % per bit.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.71-78
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• 1995

Based on the popular 4-transistor SRAM cell, an analytical expression of the minimum cell ratio was derived by modeling the static read operation. By analyzing the relatively simple expression for the minimum cell ratio, which was derived assuming the ideal transistor characteristics, effects of the changes in supply voltage and process parameters on the minimum cell ratio was predicted, and the minimum power supply voltage for read operation was determined. The results were verified by simulations utilizing the suggested simulation method, which is suitable for monitoring the lower limit of supply voltage for proper cell operation. From the analysis, it was shown that the worst condition for cell operation is low temperature and low supply voltage, and that the operation margin can be effectively improved by reducing the threshold voltage of the cell transistors.