• Title/Summary/Keyword: Low-density parity-check(LDPC) decoder

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An analysis of optimal design conditions of LDPC decoder for IEEE 802.11n Wireless LAN Standard (IEEE 802.11n 무선랜 표준용 LDPC 복호기의 최적 설계조건 분석)

  • Jung, Sang-Hyeok;Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.4
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    • pp.939-947
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    • 2010
  • The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

Evaluation of soft iterative decoder with run length limited code in optical storage system

  • 김기현;한성휴;심재성;박현수;박인식
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.99-102
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    • 2002
  • In this work, we evaluated the performance of soft iterative decoder with soft block decoder in optical storage system. Because optical storage system requires run- length limited code in general, adaptation of the soft decoders such as turbo code or LDPC(low density parity check code) is difficult without soft block decoders. The performance of the overall optical detection system is evaluated and the simplified channel detection is also proposed.

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Complexity of Distributed Source Coding using LDPCA Codes (LDPCA 부호를 이용한 실용적 분산 소스 부호화의 복호복잡도)

  • Jang, Min;Kang, Jin-Whan;Kim, Sang-Hyo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.4C
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    • pp.329-336
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    • 2010
  • Distributed source coding (DSC) system moves computational burden from encoder to decoder, so it takes higher decoding complexity. This paper explores the problem of reducing the decoding complexity of practical Slepian-Wolf coding using low-density parity check accumulate (LDPCA) codes. It is shown that the convergence of mean magnitude (CMM) stopping criteria for LDPC codes help reduce the 85% of decoding complexity under the 2% of compression rate loss, and marginal initial rate request reduces complexity below complexity minimum bound. Moreover, inter-rate stopping criterion, modified for rate-adaptable characteristic, is proposed for LDPCA codes, and it makes decoder perform less iterative decoding than normal stopping criterion does when channel characteristic is unknown.

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL

  • Hong, Jung-Hyun;Park, Joo-Yul;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.6
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    • pp.2648-2668
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    • 2016
  • Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

Equivalence of Binary Perturbation and Afterburner LDPC Decoder (이진 섭동과 에프터버너 LDPC 복호기의 동등성)

  • Lee, Hyunjae;Baek, Eun Chong;Kim, Sang-Hyo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.12
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    • pp.1742-1744
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    • 2016
  • In this letter, we prove equivalence of the Binary perturbation and Afterburner LDPC decoder that are proposed for improving the decoding performance in short length LDPC codes.

Performance of Run-length Limited Coded Parity of Soft LDPC Code for Perpendicular Magnetic Recording Channel (런-길이 제한 부호를 패리티로 사용한 연판정 LDPC 부호의 수직자기기록 채널 성능)

  • Kim, Jinyoung;Lee, Jaejin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.9
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    • pp.744-749
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    • 2013
  • We propose soft user data input on LDPC codes with parity encoded by the (1, 7) run length limited (RLL) code for perpendicular magnetic recording channel. The user data are encoded by maximum transition run (MTR) (3;11) code. In order to minimize the loss of code rate, the (1, 7) RLL code only encode the parity of LDPC. Also, to increase performance, we propose only user data part applied soft output Viterbi algorithm (SOVA). The performance using the SOVA showed good performance lower than 26 dB. In contrast, it showed worse performance high than 26 dB. This is because of incorrect soft information by high jitter noise and two different input types for LDPC decoder.

Efficient LDPC-Based, Threaded Layered Space-Time-Frequency System with Iterative Receiver

  • Hu, Junfeng;Zhang, Hailin;Yang, Yuan
    • ETRI Journal
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    • v.30 no.6
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    • pp.807-817
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    • 2008
  • We present a low-density parity-check (LDPC)-based, threaded layered space-time-frequency system with emphasis on the iterative receiver design. First, the unbiased minimum mean-squared-error iterative-tree-search (U-MMSE-ITS) detector, which is known to be one of the most efficient multi-input multi-output (MIMO) detectors available, is improved by augmentation of the partial-length paths and by the addition of one-bit complement sequences. Compared with the U-MMSE-ITS detector, the improved detector provides better detection performance with lower complexity. Furthermore, the improved detector is robust to arbitrary MIMO channels and to any antenna configurations. Second, based on the structure of the iterative receiver, we present a low-complexity belief-propagation (BP) decoding algorithm for LDPC-codes. This BP decoder not only has low computing complexity but also converges very fast (5 iterations is sufficient). With the efficient receiver employing the improved detector and the low-complexity BP decoder, the proposed system is a promising solution to high-data-rate transmission over selective-fading channels.

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Performance of LDPC Decoder of HSS based on Non-Uniform Quantization (비균일 양자화 방식 기반 HSS 방식의 LDPC 복호기 성능)

  • Kim, Tae-Hun;Kwon, Hae-Chan;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.9
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    • pp.2029-2035
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    • 2013
  • In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

A Study on Turbo Equalization for MIMO Systems Based on LDPC Codes (MIMO 시스템에서 LDPC 부호 기반의 터보등화 방식 연구)

  • Baek, Chang-Uk;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.5
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    • pp.504-511
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    • 2016
  • In this paper, MIMO system based on turbo equalization techniques which LDPC codes were outer code and space time trellis codes (STTC) were employed as an inner code are studied. LDPC decoder and STTC decoder are connected through the interleaving and de-interleaving that updates each other's information repeatedly. In conventional turbo equalization of MIMO system, BCJR decoder which decodes STTC coded bits required two-bit wise decoding processing. Therefore duo-binary turbo codes are optimal for MIMO system combined with STTC codes. However a LDPC decoder requires bit unit processing, because LDPC codes can't be applied to these system. Therefore this paper proposed turbo equalization for MIMO system based on LDPC codes combined with STTC codes. By the simulation results, we confirmed performance of proposed turbo equalization model was improved about 0.6dB than that of conventional LDPC codes.

Hybrid ARQ With Symbol Mapping Diversity and Turbo Demodulation based on LDPC Codes (심볼 맵핑 다이버시티와 터보 복조를 사용하는 LDPC 부호 기반의 Hybrid ARQ 기법)

  • Ahn, Seok-Ki;Yang, Kyeong-Cheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.9C
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    • pp.841-847
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    • 2009
  • In this paper we propose a high-performance Hybrid ARQ scheme employing Chase combining based on LDPC (Low-Density Parity-Check) codes. The proposed scheme uses symbol mapping diversity and turbo demodulation to improve decoding performance. We analyze the performance of the proposed scheme by EXIT (EXtrinsic Information Transfer) chart and compare its performance with several symbol mappings.