• Journal of Information Processing Systems
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• v.9 no.1
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• pp.41-52
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• 2013

One of the obstacles preventing the Zigbee protocol from being widely used is the excessive power consumption of Zigbee devices in low bandwidth and low power requirement applications. This paper proposes a protocol that resolves the power efficiency problem. The proposed protocol reduces the power consumption of Zigbee devices in beacon-enabled networks without increasing the time taken by Zigbee peripherals to communicate with their coordinator. The proposed protocol utilizes a beacon control mechanism called a "sleep pattern," which is updated based on the previous event statistics. It determines exactly when Zigbee peripherals wake up or sleep. A simulation of the proposed protocol using realistic parameters and an experiment using commercial products yielded similar results, demonstrating that the protocol may be a solution to reduce the power consumption of Zigbee devices.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.

• Journal of Power Electronics
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• v.11 no.4
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• pp.527-532
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• 2011

Due to the need for improved fuel consumption and the trend towards increasing the electrical content in automobiles, integrated starter generator (ISG) systems are being considered by the automotive industry. In this paper, in order to change the conventional generator of a vehicle, a belt driven integrated starter generator is considered. The overall ISG system, the design considerations for the claw pole type AC electric machine and a low voltage very high current power stage implementation are discussed. Test data on the low voltage claw pole type machine is presented, and a large current voltage source DC/AC inverter suitable for low voltage integrated starter generator operation is also presented. A metal based PCB (Printed Circuit Board) power unit to attach the 4-parallel MOS-FETs is used to achieve extremely high current capability. Furthermore, issues related to the torque assistance during vehicle acceleration and the generation/regeneration characteristics are discussed. A prototype with the capability of up to 1000 A and 27 V is designed and built to validate the kilo-amp inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.363-368
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• 2015

This paper deals with an improved current source using full-bridge converter type for thyristor valve test of HVDC system. The conventional high-current and low-voltage source of synthetic test circuit requires additional auxiliary power supply to provide the reverse voltage for the auxiliary thyristor valve during turn-off process. The proposed circuit diagram to provide the reverse voltage is extremely simple because no additional component is required. The reverse voltage can be obtained from the input DC voltage of the high-current and low-voltage power supply. The operation principle and design method of the proposed system are described. Simulation and experimental results in scaled down STC of 200 V, 30 A demonstrate the validity of the proposed scheme.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1459-1473
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• 2018

This paper focuses on voltage control schemes for multi-terminal low-voltage direct current (LVDC) distribution systems. In a multi-terminal LVDC distribution system, there can be multiple AC/DC converters that connect the LVDC distribution system to the AC grids. This configuration can provide enhanced reliability, grid-supporting functionality, and higher efficiency. The main applications of multi-terminal LVDC distribution systems include flexible power exchange between multiple power grids and integration of distributed energy resources (DERs) using DC voltages such as photovoltaics (PVs) and battery energy storage systems (BESSs). In multi-terminal LVDC distribution systems, voltage regulation is one of the most important issues for maintaining the electric power balance between demand and supply and providing high power quality to end customers. This paper focuses on a voltage control method for multi-terminal LVDC distribution system that can efficiently coordinate multiple control units, such as AC/DC converters, PVs and BESSs. In this paper, a control hierarchy is defined for undervoltage (UV) and overvoltage (OV) problems in LVDC distribution systems based on the control priority between the control units. This paper also proposes methods to determine accurate control commands for AC/DC converters and DERs. By using the proposed method, we can effectively maintain the line voltages in multi-terminal LVDC distribution systems in the normal range. The performance of the proposed voltage control method is evaluated by case studies.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.4
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• pp.195-204
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• 2013

The embedded software has been developed in the forms of various versions that provides similar service based on product family. For increase usefulness of product family, software must has well-structured and reusable properties. Software architecture is important to improve adaptability in model-based development of embedded software mounted onto product family. In this paper, we proposed a technique of ADD(Attribute-Driven Design)-based software architecture design for low power software development. This technique provides a chance to consider the power consumption issue in design phase of software, and makes possible to develop low power embedded software.