• ETRI Journal
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• v.44 no.5
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.458-465
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• 2013

This paper proposes a novel soft-switched auxiliary resonant circuit to provide a Zero-Voltage-Transition at turn-on for a conventional PWM boost converter in a PFC application. The proposed auxiliary circuit enables a main switch of the boost converter to turn on under a zero voltage switching condition and simultaneously achieves both soft-switched turn-on and turn-off. Moreover, for the purpose of an intelligent multi-chip power module fabrication, the proposed circuit is designed to satisfy several design constraints including space saving, low cost, and easy fabrication. As a result, the circuit is easily realized by a low rated MOSFET and a small inductor. Detail operation and the circuit waveform are theoretically explained and then simulation and experimental results are provided based on a 1.8 kW prototype PFC converter in order to verify the effectiveness of the proposed circuit.

• Transactions on Electrical and Electronic Materials
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• v.1 no.3
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• pp.1-5
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• 2000

This paper presents a new sort of multilayer piezoelectric ceramic transformer for switching regulation power supplies. This piezoelectric transformer operate in the second thickness resonant vibration mode. Accordingly its resonant frequency is higher than 1 NHz, Because output power is low if input and output part of transformer are consisted of single layer, this research suggests a new method, which is consisted of both input and output part of transformer have 2-layered piezoelectric ceramics, The size of transformer is 20 mm in width and length, and 1.4 mm in thickness, respectively, To design a high efficient switching circuit of the transformer, internal circuit parameters were measured and then weve calculated a parameter of inductor nd capacitor to design a driving circuit, Weve used a MISFET and its driver circuit modified a calp oscillator circuit as the primary switching circuit.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.601-604
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• 2004

In this paper, we propose a driving circuit that can be operated with a lower voltage than that of the conventional circuit without reducing the discharge voltage. the circuit proposed in this paper has a merit to improve the electrical characteristics because it can be composed of switching devices with low voltage. The operation and efficiency using real devices. The features of the circuit proposed in this paper are as follows; the power loss can be decreased by the use of low voltage, the cost if the driving circuit for PDP can be reduced by the use of switching devices operated with low voltage.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.723-727
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• 2004

A new high-performance and low cost single switch energy recovery display driver for an AC plasma display panel (PDP) is proposed. Since it is composed of only one auxiliary power switch, two small inductors, and eight diodes compared with the conventional circuit consisting of four auxiliary power switches, two small inductors, eight power diodes, and two external capacitors, it features a much simpler structure and lower cost. Nevertheless, since the rootmean-square (RMS) value of the inductor current is very small, it also has very desirable advantages such as n low conduction loss and high efficiency. Furthermore, there are no serious voltage-drops caused by the large gas-discharge current with the aid of the discharge current compensation, which can also greatly reduce the current flowing through power switches and maintain the panel to light at n lower sustaining voltage. In addition, all main power switches are turned on under the zero-voltage switching (ZVS) and thus, the proposed circuit has a improved EMI, increased reliability, and high efficiency. Therefore, the proposed circuit will be well suited to the wall hanging PDP TV. To confirm the validity of the proposed circuit, circuit operations, features,and design considerations are presented and verified experimentally on a 6-inch PDP, 50kHz-switching frequency, and sustaining voltage 141V based prototype.