• 전기학회논문지
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• 제61권10호
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• pp.1432-1441
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• 2012

In this study, an improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source inverter(Improved LCCT ZSI) with characteristics of Quasi Z-source inverter(QZSI) and LCCT Z-source inverter(LCCT ZSI) is proposed. The proposed inverter can also reduce the voltage stress and input current/capacitor voltage ripples compared with conventional LCCT ZSI and Quasi ZSI. A two winding trans in Z-impedance network of the conventional LCCT ZSI is replaced by a three winding trans in the proposed inverter. To verify the validity of the proposed inverter, a DSP controlled hardware was made and PSIM simulation was executed for each method. Comparing the current and voltage ripples of each method under the condition of input DC voltage 70[V] and output AC voltage 76[Vrms], the input current and capacitor voltage ripple factors of the proposed inverter were low as 11[%] and 1.4[%] respectively. And, for generation of the same output AC voltage of each method, voltage stress of the proposed inverter was low as 175[V] under the condition of duty ratio D=0.15. As mentioned above, we could know that the proposed inverter have the characteristics of low voltage stress, low ripple factor and low operation duty ratio compared with the conventional methods. Finally, the efficiency according to load change/duty ratio and the transient state characteristics were discussed.

• Journal of Power Electronics
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• 제19권3호
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• pp.665-675
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• 2019

Renewable energy based on photovoltaic systems is beginning to play an important role to supply power to remote areas all over the world. Owing to the lower output voltage of photovoltaic arrays, high gain DC-DC converters with a high efficiency are required in practice. This paper presents a novel interleaved DC-DC boost converter with a high voltage gain, where the input terminal is interlaced in parallel and the output terminal is staggered in series (IPOSB). The IPOSB configuration can reduce input current ripples because two inductors are interlaced in parallel. The double output capacitors are charged in staggered parallel and discharged in series for the load. Therefore, IPOSB can attain a high step-up conversion and a lower output voltage ripple. In addtion, the output voltage can be automatically divided by two capacitors, without the need for extra sharing control methods. At the same time, the voltage stress of the power devices is lowered. The inrush current problem of capacitors is restrained by the inductor when compared with high gain converters with a switching-capacitor structure. The working principle and steady-state characteristics of the converter are analyzed in detail. The correctness of the theoretical analysis is verified by experimental results.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권12호
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• pp.813-820
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• 2000

A technique to suppress the low frequency ripple voltage of the DC output in three phase buck diode converter is presented in this paper. The proposed pulse frequency modulation methods and duty ratio modulation methods are employed to regulate the output voltage of the buck diode converter and guarantee zero-current-switching(ZCS) of the switch over the wide load range. The proposed control methods used in this paper provide generally good performance such as low THD of the input line current and unity power factor. In addition, control methods can be effectively used to suppress the low frequency ripple voltage appeared in the dc output voltage. The harmonic injection technique illustrates its validity and effectiveness through the simulations and experiments.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.542-546
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• 2004

This paper presents a technique to reduce the low frequency ripple voltage of the dc output in a BIFRED converter with a small-sized energy storage capacitor. The proposed pulse width control method can be effectively used to suppress the low frequency ripple appeared in the dc output and still shows generally good performance such as low THD of input line current and high power factor. Using the small-sized energy storage capacitor, it has better merits of low cost and small size than a conventional BIFRED converter. The proposed technique is illustrated its validity and effectiveness through simulations.

• Journal of Power Electronics
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• 제5권3호
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• pp.190-197
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• 2005

This paper presents a technique to reduce the low frequency ripple voltage of the dc output in a BIFRED converter with a small-sized energy storage capacitor. The proposed pulse width control method can be effectively used to suppress the low frequency ripple appeared in the dc output and still maintains generally good performance such as low THD of input line current and a high power factor. Using the small-sized energy storage capacitor, it has better merits of low cost and smaller size than a conventional BIFRED converter. The proposed technique is illustrated its validity and effectiveness through simulations.

• 전기학회논문지
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• 제57권6호
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• pp.1003-1011
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• 2008

In this paper, optimal design of interleaved boost converters is studied in order to design low ripple, size, loss and high performance converters for fuel cell applications. Also, the process of optimal design of interleaved boost converter has been performed. Input current ripple, output voltage ripple, losses and capacity of electrical components are theoretically analyzed and informative simulation and experimental results are provided.

• Journal of Power Electronics
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• 제10권3호
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• pp.328-333
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• 2010

A photovoltaic power conditioning system (PV PCS) that contains single-phase dc/ac inverters tends to draw an ac ripple current at twice the output frequency. Such a ripple current perturbs the operating points of solar cells continuously and it may reduce the efficiency of the current based maximum power point tracking technique (CMPPT). In this paper, the ripple current generation in a dc link and boost inductor is analyzed using the ac equivalent circuit of a dc/dc boost converter. A new feed-forward ripple current compensation method to incorporate a current control loop into a dc/dc converter for ripple reduction is proposed. The proposed feed-forward compensation method is verified by simulation and experimental results. These results show a 41.8 % reduction in the peak-to peak ac ripple. In addition, the dc/ac inverter control system uses an automatic voltage regulation (AVR) function to mitigate the ac ripple voltage effect in the dc link. A 3kW PV PCS prototype has been built and its experimental results are given to verify the effectiveness of the proposed method.

• 전력전자학회논문지
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• 제17권2호
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• pp.182-189
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• 2012

In this paper, the input current and output voltage ripple of the soft switching interleaved boost converter was analyzed. Ripples of input current and output voltage with an interleaved method is analysed and as a result, the facts that it has lower ripple current than conventional interleaved method is verified. it means that a capacity of a main inductor can be reduced. Besides, a low capacitance of capacitor which means high lifetime and confidence can be used because of reducing ripples of output voltage. In order to verify the validity of the proposed converter used 10uF film capacitor, experiment was performed, and the efficiency of the proposed converter was measured with variable load and duty conditions.

• Journal of Power Electronics
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• 제15권2호
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• pp.327-337
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• 2015

This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.

• 산업기술연구
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• 제32권A호
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• pp.115-118
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• 2012

Recently, there are a lot of papers in order to replace the electrolytic capacitor into the film capacitor in output of PFC(Power Factor Correction). However, the film capacitor, which has capacitance of low values, causes a large ripple voltage in output of PFC. The LED drivers are connected series in the output of PFC and affected by the magnitude of voltage ripple. In this paper, we have compared the fixed frequency method with the variable frequency for the constant-current control and propose the control method to avoid the sub-harmonic oscillation in the variable input voltage. An 80W PFC, using film capacitors instead of electrolytic capacitors, and LED driver has been built and compared the fixed frequency control method with the variable frequency control method.