• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.117-120
• /
• 1988

A new current source inverter (CSl) with dc-side commutation and load-side energy recovery circuit is proposed with analysis and explanation of the circuit operation. Proposed inverter overcomes the most drawbacks of the conventional CSI's - high device voltage stress, low operating frequency range, large commutation capacitance, etc. - by employing simultaneous recovery and commutation concept. The new CSI employs only one commutation capacitor and it can be built with considerably low cost. The commutation energies are temporarily stored into a large dc capacitor and recovered to the load side, thus the device voltage stress is low and the efficiency is high in the proposed inverter. Computer simulation results are given at the steady state, and a guideline determining the commutation circuit is given.

• Proceedings of the KIEE Conference
• /
• 2000.07d
• /
• pp.3201-3204
• /
• 2000

In general, analog tester or strip chart recorder have been used to measure the corrosion potential of structures such as gas pipelines, oil pipelines, hot water pipelines, power cables etc. Recently, automatic digital data logger substitutes for these manual equipment because using these manual equipments are tedious and time consuming. However, digital data logger also has a shortcoming, that is, short measuring time because of the short lifetime of batteries. Therefore, we developed a long lifetime and low power loss battery taking advantage of galvanic series. In this paper, the results of development for power generator using two metals and DC/DC converter in order to obtain enough voltage for the operation of digital data logger. DC/DC converter operates with 0.5[V]. Its output voltage is 3.5[V] and output current is from 60[mAh] to 1,200[mAh].

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.6
• /
• pp.51-57
• /
• 1997

Low-voltage, low-power gm-C filter utilizing newly dveloped operational transconductance amplifier (OTA) is described in this paper. The OTA has only two MOS transistors in saturation region between $V_{DD}$ and GND, and thus low voltage operation is possible. To improve the linearity, the OTA is made differential. Common mode feedback, essential in differential circuit, requires no additional implemented in $0.8\mu\textrm{m}$ CMOS process, and the center frequency can be controlled from 15MHz with 3.0V single power supply.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3184-3186
• /
• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• Journal of IKEEE
• /
• v.25 no.2
• /
• pp.309-314
• /
• 2021

The proposed preamplifier for the static random access memory reduces the time required for the sense amplifier enable during the read operation by 55%, which leads to a significant speed up the total spped. This is attirbuted to the novel circuit techqniue that cancels out the transistor mismatch which is induced by the process variation. In addition, a selective enable circuit for preamplifier circuit is proposed, so the proposed preamplifier is enabled only when it is required. Accordingly the energy overhead is limited below 4.45%.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.216-224
• /
• 2020

This paper proposes an impedance design method of the test device for evaluating Low Voltage Ride Through(LVRT) and High Voltage Ride Through(HVRT) functions. The LVRT/HVRT test device should have ability to generate the fault voltage specified in the grid code for a certain period and to limit the magnitude of the fault current with the design specification. In this paper, the impedance design method for auto transformer is proposed based on a equivalent model of a tap-change auto-transformer during LVRT/HVRT operation. In addition, to generate various fault voltages required the LVRT/HVRT test, tap impedance design in the auto transformer is considered. To verify the validity of the proposed design method, the design process of the 10MVA LVRT/HVRT test device was conducted and the design results was verified through simulation models.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2722-2728
• /
• 2011

3Phase PWM rectifier has become increasingly popular due to its capability of nearly sinusoidal waveform of the input current, and nearly unity power factor operation as a AC/DC rectifier of high capacity telecommunication power supply system. Generally, PI controller is used as a voltage controller of PWM rectifier and voltage controller must be designed to have low overshoot in transient state to get a reliability and stable operation. However, in the application of telecommunication in which load condition is varied very fast, the voltage controller must have a large bandwidth to reduce output voltage variation. The PI controller with large bandwidth arouse the excessive overshoot of the output voltage, and this large output voltage variation degrades the reliability of communication power of the three-phase PWM Rectifier. In this paper, new IP voltage controller for 3 phase PWM rectifier is proposed which has relatively low transient output voltage variation. The improved output characteristics of the transient state voltage responses of the starting and at load changes of the proposed voltage controller are proved by simulations and experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.1-6
• /
• 2006

This paper proposes substrate-bias voltage generator to reduce leakage power consumption of digital logic circuits operating at supply voltage of 0.5V. Proposed substrate-bias voltage generator is composed of VSS and VBB generator. The former circuit produces negative voltage and supplies its output voltage for VBB generator. As a result VBB generator develops much lower negative voltage than that of conventional one. Proposed circuit is fabricated using 0.18um 1Poly-6Metal CMOS process and measurement result demonstrated stable operation with substrate-bias voltage of -0.95V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.2
• /
• pp.111-124
• /
• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.2
• /
• pp.345-352
• /
• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.