• 한국전기전자재료학회논문지
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• 제21권2호
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• ETRI Journal
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• 제19권2호
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• 전자공학회논문지
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• 제51권1호
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• pp.52-56
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• 2014

본 논문은 고효율 전력증폭기는 무선전력전송을 위한 게이트와 드레인 바이어스 조절 회로를 사용하여 설계하였다. 이 조절 회로는 PAE (Power Added Efficiency)를 개선하기 위해 사용되었다. 게이트와 드레인 바이어스 조절 회로는 directional coupler, power detector, and operational amplifier로 구성되어있다. 구동증폭기를 사용하여 고이득 2단 증폭기는 전력증폭기의 낮은 입력단에 사용되었다. 게이트와 드레인 바이어스 조절회로를 사용하여 제안된 전력증폭기는 낮은 전력에서 높은 효율성을 가질 수 있다. PAE는 80.5%까지 향상되었고 출력전력은 40.17dBm이다.

• Journal of Advanced Marine Engineering and Technology
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• 제32권8호
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.687-694
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• 2008

This paper is focused on the improvement of MOS device reliability related to deuterium process. The injection of deuterium into the gate oxide film was achieved through two kind of method, high-pressure annealing and low-energy implantation at the back-end of line, for the purpose of the passivation of dangling bonds at $SiO_2/Si$ interface. Experimental results are presented for the degradation of 3-nm-thick gate oxide ($SiO_2$) under both negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) stresses using P and NMOSFETs. Annealing process was rather difficult to control the concentration of deuterium. Because when the concentration of deuterium is redundant in gate oxide excess traps are generated and degrades the performance, we found annealing process did not show the improved characteristics in device reliability, compared to conventional process. However, deuterium ion implantation at the back-end process was effective method for the fabrication of the deuterated gate oxide. Device parameter variations under the electrical stresses depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to conventional process. Our result suggests the novel method to incorporate deuterium in the MOS structure for the reliability.

• 한국전자파학회논문지
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• 제28권6호
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• pp.435-443
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• 2017

본 논문에서는 cascode 구조가 적용된 Class-E 스위칭 모드 CMOS 전력증폭기의 common-gate 트랜지스터 게이트 바이어스 효과에 대해 분석하였다. 게이트 바이어스 효과를 확인하기 위해서 전력증폭기의 DC 전력소모, 효율을 분석하였다. 분석 결과를 통해서 전력증폭기의 최고 효율을 보여주는 common-gate 트랜지스터의 게이트 바이어스가 일반적으로 사용하는 전력증폭기 전원 전압보다 낮음을 확인하였다. 트랜지스터의 게이트 바이어스가 계속 감소함에 따라 on-저항을 확인하여 커지고, 이에 따라 출력, 효율이 감소하는 것도 확인하였다. 이 두 가지 현상을 통해 게이트 바이어스가 스위칭 모드 전력증폭기에 미치는 영향을 분석하였다. 이 분석을 증명하기 위해서 $0.18{\mu}m$ RF CMOS 공정으로 1.9 GHz 스위칭 모드 전력증폭기를 설계하였다. 앞에서 설명한 것처럼 전력증폭기의 최대 효율은 전력증폭기의 인가 전압(3.3 V)보다 낮은 2.5 V에서 확인할 수 있었다. 이 때 최고 출력은 29.1 dBm, 최고 효율은 31.5 %이다. 측정 결과를 통해서 스위칭 모드 전력증폭기 common-gate 트랜지스터의 게이트 바이어스 효과를 실험적으로 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.