• Journal of IKEEE
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• v.23 no.3
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• pp.994-1002
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• 2019

In this paper, we propose the development of a power conversion system for electric power take-off (e-PTO) of agricultural electric vehicles. Most e-PTOs use commercial power $220V_{AC}$. A bidirectional power conversion system having a two-stage structure consisting of a DC-DC converter and a DC-AC inverter for supplying a high output voltage using a low battery voltage of an agricultural electric vehicle is suitable. we propose a power conversion system consisting of the one-stage dual active bridge (DAB) converter and the two-stage bidirectional full bridge inverter. In addition, we propose a soft start algorithm for reducing the inrush current generated by the link capacitor charging during the initial operation. A 3kW prototype system and its corresponding algorithms have been implemented to verify its effectiveness through experiments.

• Journal of Power Electronics
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• v.19 no.3
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• KIEE International Transactions on Electrophysics and Applications
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• v.12C no.4
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• pp.208-213
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• 2002

The present study describe the electrical performance of amorphous T $a_2$ $O_{5-X}$ fabricated on the buffer layers Ti and Ti $O_2$. T $a_2$ $O_{5-X}$ thin films were grown on the Ti and Ti $O_2$ layers as a capacitor layer using reactive sputtering method. The X-ray pattern analysis indicated that the two as-deposited films were amorphous and the amorphous state was kept stable on the RTA(rapid thermal annealing) at even $700^{\circ}C$. Measurements of dielectric properties of the reactive sputtered T $a_2$ $O_{5-X}$ thin films fabricated in two simple MIS(metal insulator semiconductor), structures, (Cu/T $a_2$ $O_{5}$ Ti/Si and CuT $a_2$ $O_{5}$ Ti $O_2$Si) show that the amorphous T $a_2$ $O_{5}$ grown on Ti showed high dielectric constant (23～39) and high leakage current density(10$^{-3}$ ～10$^{-4}$ (A/$\textrm{cm}^2$)), whereas relatively low dielectric constant (～15) and tow leakage current density(10$^{-9}$ ～10$^{-10}$ (A/$\textrm{cm}^2$)) were observed in the amorphous T $a_2$ $O_{5}$ deposited on the Ti $O_2$ layer. The electrical behaviors of the T $a_2$ $O^{5}$ thin films were attributed to the contribution of Ti- $O_2$ and the compositionally gradient Ta-Ti-0, being the low dielectric layer and high leakage current barrier. In additional, The T $a_2$ $O_{5}$ Ti $O_2$ thin films exhibited dominant conduction mechanism contributed by the Poole-Frenkel emission at high electric field. In the case of T $a_2$ $O_{5}$ Ti $O_2$ thin films were related to the diffusion of Ta, Ti and O, followed by the creation of vacancies, in the rapid thermal treated thin films.films.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.800-807
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• 2006

To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.585-588
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• 2014

This paper presents a self-powered sensor node circuit using photovoltaic and vibration energy harvesting. The harvested energy from a solar cell and a vibration device(PZT) is stored in a storage capacitor. The stored energy is managed by a PMU(Power Management Unit). In order to supply a stable voltage to the sensor node, an LDO(Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter), and 10-bit digital output data corresponding to current temperature is obtained. The proposed circuit is designed in a 0.35um CMOS process, and the designed chip size including PADs is $1.1mm{\times}0.95mm$.