• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.304-315
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• 2013

In this paper, analysis of cascaded H-bridge multilevel inverter in DTC-SVM (Direct Torque Control-Space Vector Modulation) based induction motor drive for FCEV (Fuel Cell Electric Vehicle) is presented. Cascaded H-bridge multilevel inverter uses multiple series units of H-bridge power cells to achieve medium-voltage operation and low harmonic distortion. In FCEV, a fuel cell stack is used as the major source of electric power moreover the battery and/or ultra-capacitor is used to assist the fuel cell. These sources are suitable for utilizing in cascaded H-bridge multilevel inverter. The drive control strategy is based on DTC-SVM technique. In this scheme, first, stator voltage vector is calculated and then realized by SVM method. Contribution of multilevel inverter to the DTC-SVM scheme is led to achieve high performance motor drive. Simulations are carried out in Matlab-Simulink. Five-level and nine-level inverters are applied in 3hp FCEV induction motor drive for analysis the multilevel inverter. Each H-bridge is implemented using one fuel cell and battery. Good dynamic control and low ripple in the torque and the flux as well as distortion decrease in voltage and current profiles, demonstrate the great performance of multilevel inverter in DTC-SVM induction motor drive for vehicle application.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.131-136
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• 2015

This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.99-105
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• 2004

A shared-capacitor charge-sharing ROM (SCCS-ROM) using dummy bit lines is proposed. The SCCS-ROM reduces the bit line swing voltage using the charge-sharing technique of the conventional charge-sharing ROM (CS-ROM). Although the CS-ROM needs three small capacitors per output bit, the proposed SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. A SCCS-ROM with 8K${\times}$15bits implemented in a 0.35${\mu}{\textrm}{m}$ CMOS process. The SCCS-ROM consumes 8.63㎽ at 100MHz with 3.3V The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.640-647
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• 1995

In this study, the BaTiO$\sub$3/ capacitor add to MnO$\sub$2/ like depressor and shifter were investigated for temperature or voltage compensation by structural and electrical analysis. The relative density of BCTM, generating poly crystall and formation of lattice defect, has a 90[%] over as the CaTiO$\sub$3/ come out to control grain size. The current density of BCTM2 increased non-ohmic in high-electric field but that BCTM3 and BCTM4 had a few changing. The BCTM3 and BCTM4 unformated grain boundary shown temperature compensation properties, so that the dielectric constant was low value. The curie point was near 140[.deg. C] in BCTM1 and BCTM4, but BCTM3 and BCTM4 not shown the curie point. It is found that the charging energy of BCTM4 was changed 6[%] according to rising temperature from room temperature to 417[K]. The formation of BaMnO$\sub$3/ was low dielectric constant to change frequency and temperature.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.1-8
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• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1571-1576
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• 2016

A Tesla coil is an electrical resonant transformer circuit invented by Nikola Tesla in 1891. It is used to produce high-voltage, low-current, high frequency alternating-current electricity. Tesla coil can generate a long streamer with several million volts of electricity as a high voltage device. It is basically consists of a voltage transformer, high voltage capacitor, spark gap, primary coil, secondary coil and toroid. It is difficult to appear in the output size of the streamer is controlled by the spark gap. The general decision method of the length of streamer is to display the electric output in accordance with the design specifications in initial development plan. Design specifications and the electric output is determined by the application of facilities. In this paper the spark gap is replaced with periodic switching semiconductor device to control output voltage easily in order to apply overvoltage protective circuit due to a secondary coil and a performance test. In these days, their main use is for entertainment and educational displays of the museum, although small coils are still used as leak detectors for high vacuum systems.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.521-526
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• 1999

It was investigated that traps were generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The charge state of the traps can easily be changed by application of low voltage after the stress high voltage. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$to 814$\AA$ with capacitor areas of $10^{-3}{$\mid$textrm}{cm}^2$. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2528-2530
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• 2000

In general, Diode makes a major role in electronic circuit. For example, switching of rectifier, cross current of switching rectifier, energy transfer of electronic element and reverse charge of capacitor, voltage insulation, energy feedback from load to power supply, and such as recovery of storaged energy. Generally, We regard power diode as ideal element, but it has a certain boundary actually, specially, We use diode for detecting circuit peak hold voltage signal. It has cut in voltage. It occurs error of measurement value namely. This error, below in region diode voltage drop (0.7v) measurement value is wholesome signal, Specially, We can not get precision data. Therefore, precision level is low between theoretical and measurement data because of error in actual circuit. Conclusionally, In this paper, We define the error concerning to the power diode characteristics which is used detecting of the minute signal, and recommend the method that minimize measurement error.