• 전력전자학회논문지
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• 제22권3호
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• pp.185-192
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• 2017

This paper proposes a single-stage interleaved soft-switching electrolytic capacitor-less EV charger with reduced component count and simple circuit structure. The proposed charger achieves ZVS turn-on of all switches and ZCS turn-off of all diodes without regard to voltage and load variation. It achieves high power density even without an input filter due to CCM operation and bulky electrolytic capacitors and without a low-frequency component in the transformer. A 2 kW prototype of the proposed charger with sinusoidal charging is built and tested to verify the validity of the proposed operation.

• 조명전기설비학회논문지
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• 제22권9호
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• pp.25-31
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• 2008

유도전동기의 자계는 전류의 방향에 따라 자화 및 감자되는 특성을 가지고 있다. 전통기의 자계를 형성하는데 필요한 자화전류는 유도성으로 무효전력의 대부분을 차지하고 있다. 무효전력은 유도전동기가 동작하는데 필요한 자계를 지속시키는 역할을 한다. 유도전통기의 역률은 낮은 편이므로 역률 보상이 필요하다. 유도전동기를 정격출력보다 낮은 부하로 운전할 경우 유효전력에 비해 무효성분의 비율증가로 역률이 낮아진다. 역률 보상장치의 용량은 전동기 정격에 맞도록 설치하기를 권고하고 있다. 그러나 부하의 운전상황에 따라 역률 보상용 커패시터 값은 수정하기가 어렵다. 본 논문에서는 저압 소용량 유도 전동기에 연결된 부하의 변화에 따라 전력 및 역률의 동작특성을 해석한 결과 기존에 제시된 낮은 역률 보상용 파라미터는 수정되어야 함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.45-45
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• 2007

Capacitors among the embedded passive components are most widely studied because they are the major components in terms of size and number and hard to embed compared with resistors and inductors due to the more complicated structure. To fabricate a capacitor-embedded PCB for in-line process, it is essential to adopt a low temperature process (<$200^{\circ}C$). However, high dielectric materials such as ferroelectrics show a low permittivity and a high dielectric loss when they are processed at low temperatures. To solve these contradicting problems, we studied BMN materials as a candidate for dielectric capacitors. processed at PCB-compatible temperatures. The morphologies of BMN thin films were investigated by AFM and SEM equipment. The electric properties (C-F, I-V) of Pt/BMN/Cu/polymer were evaluated using an impedance analysis (HP 4194A) and semiconductor parameter analyzer (HP4156A). $Bi_2Mg_{2/3}Nb_{4/3}O_7$(BMN) thin films deposited on copper clad laminate substrates by sputtering system as a function of Ar/$O_2$ flow rate at room temperature showed smooth surface morphologies having root mean square roughness of approximately 5.0 nm. 200-nm-thick films deposited at RT exhibit a dielectric constant of 40, a capacitance density of approximately $150\;nF/cm^2$, and breakdown voltage above 6 V. The crystallinity of the BMN thin films was studied by TEM and XRD. BMN thin film capacitors are expected to be promising candidates as embedded capacitors for printed circuit board (PCB).

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.48.1-48.1
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• 2009

Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.708-712
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• 2001

A new phase-shifted parallel-input/series-output (PI SO) dual inductor-fed push-pull converter for high-power step­up applications is proposed. This converter is operated at a constant duty cycle and employs an auxiliary circuit to control the output voltage with a phase-shift between the two modules. It features a voltage conversion characteristic which is linear to changes in the control input, and high step-up ratio with a greatly reduced switch turn-off stress resulting in a significant increase in the converter efficiency. It also shows a low ripple content and low root-mean-square (RMS) current in the output capacitor. The operational principle is analyzed and a comparative analysis with the conventional pulse-width-modulated (PWM) PISO dual inductor-fed push-pull converter is presented. A 50kHz, 800W, 350Vdc prototype with an input of 20-32Vdc has also been constructed to validate the proposed converter. The proposed converter compares favorably with the conventional counterpart and is considered well suited to high-power step-up applications.

• Journal of Power Electronics
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• 제15권6호
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• 전기학회논문지P
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• 제57권2호
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• pp.121-126
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• 2008

This paper analyzes the losses of a Steinmetz connection three-phase induction motor which is supplied by a single-phase source. The T-type equivalent circuit which is taken no-load losses into account is used to determine phase converter capacitive reactances at starting and rated speed by using the condition of the minimum voltage unbalance. The starting and the operating capacitor are replaced at the slip of the same voltage unbalance factor points which are depicted using two capacitive reactances. The operation characteristics are investigated by comparing with those of three-phase balanced operation to find the feasibility of single-phase operation. To analyze the losses of this motor, the output power decrease factor(OPDF), the loss ratio(LR), the no load loss ratio(NLLR), the copper loss ratio(CLR), the stator copper loss ratio(SCLR), and the rotor copper loss ratio(RCLR) are defined and simulated in the whole slip range. The simulated results show that OPDF is maintained almost uniformly, LR is low at low speed and high at high speed, CLR is higher !ban NLLR, but CLR varies concavely and NLLR varies convexly at high speed, SCLR is low at low speed and high at high speed, but SCLR varies convexly at high speed, and RCLR is nearly opposite to SCLR.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.25.2-25.2
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• 2011

Recently, thin film capacitors used for vehicle inverters are small size, high capacitance, fast response, and large capacitance. But its applications were made up of liquid as electrolyte, so its capacitors are limited to low operating temperature range and the polarity. This research proposes using Ni-P alloys by electroless plating as the electrode instead of liquid electrode. Our substrate has a high aspect ratio and complicated shape because of anodic aluminum oxide (AAO). We used AAO because film thickness and effective surface area are depended on for high capacitance. As the metal electrode instead of electrolyte is injected into AAO, the film capacitor has advantages high voltage, wide operating temperature, and excellent frequency property. However, thin film capacitor made by electroless-plated Ni on AAO for full-filling into etched tunnel was limited from optimizing the deposition process so as to prevent open-through pore structures at the electroless plating owing to complicated morphological structure. In this paper, the electroless plating parameters are controlled by temperature in electroless Ni plating for reducing reaction rate. The Electrical properties with I-V and capacitance density were measured. By using nickel electrode, the capacitance density for the etched and Ni electroless plated films was 100 nFcm-2 while that for a film without any etch tunnel was 12.5 nFcm-2. Breakdown voltage and leakage current are improved, as the properties of metal deposition by electroless plating. The synthesized final nanostructures were characterized by scanning electron microscopy (SEM).

• 전자공학회논문지
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• 제50권12호
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• pp.63-70
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• 2013

본 논문은 외부 커패시터 없이 광범위 하게 높은 전원 공급 잡음 제거비(PSRR)을 갖는 선형 정류기(LDO)에 관한 것이다. 제안된 LDO는 높은 PSRR과 안정도를 유지하기 하기 위해 nested Miller 보상 기술을 사용하였고, 내부적으로 캐스코드(cascode) 보상과 전류버퍼(current buffer) 보상 기술을 사용하였다. 또한 외부의 부하 커패시터가 없기 때문에 외부 하드웨어 비용을 최소화 하였고, 제안된 보상 기법을 사용하여 내부에 작은 커패시터를 사용하고도 안정도를 확보할 수 있었다. 설계된 LDO는 2.5V~4.5V의 입력 전압을 받아서 1.8V의 전압을 출력하고 최대 10mA의 부하 전류를 구동할 수 있다. 일반 0.18um CMOS 공정을 이용하여 제작하였고 면적은 300um X 120um 이다. 측정된 PSRR은 DC일 때 -76dB, 1MHz일 때 -43dB를 만족한다. 동작 전류는 25uA를 소모한다.