• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• 국제물리치료학회지
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• 제2권2호
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• pp.318-323
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• 2011

The purpose of this study identify that spinal decompression therapy effect on and pain, length Of leg distance(LLD), and muscle power and flexibility in patient with low back pain. The participants is 20 female and male with low back pain, and participant assign to decompression therapy group and control group at random. The decompression therapy apply to 20 minute 3 time for a week during 4 weeks. The Measurement items is pain, LLD, and muscle power, flexibility. The comparison between the before and after was Wilcoxon's U test, and 2 group after spinal decompression therapy application compared Mann-Whithney U test. Spinal decompression therapy reduced statistically significance the pain, LLD, and increased statistically significance the muscle power and flexibility increased the muscle power(p<.05). This study showed that spinal decompression therapy does affect pain, LLD, and muscle power and flexibility in patient with low back pain.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.601-604
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• 1996

It is well known that steam generator water level control at low power operation has many difficulties in a PWR (pressurized water reactor) nuclear power plant. The reverse process responses known as shrink and swell effects make it difficult to control the steam generator water level at low power. A new automatic control logic to remove the reverse process responses is proposed in this paper. It is implemented in PLC (programmable logic controller) and evaluated by using test equipment in Korea Atomic Energy Research Institute. The simulation test shows that the performance requirements is met at low power (below 15%). The water level control by new control logic is stabilized within 1% fluctuation from setpoint, while the water level by YGN 3 and 4 control logic is unstable with the periodic fluctuation of 25% magnitude at 5% power.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.892-895
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• 2011

SoC(System-On-Chip)을 테스트 하는 동안 소모하는 전력소모는 SoC내의 IP 코어가 증가됨에 따라 매우 중요한 요소가 되었다. 본 논문에서는 Scan Latch Reordering과 Clock Gating 기법을 적용하여 scan-in 전력소모를 줄이는 알고리즘을 제안한다. Scan vector들의 해밍거리를 최소로 하는 새로운 Scan Latch Reordering을 적용하였으며 Gated scan 셀을 사용하여 저전력을 구현하였다. ISCAS 89 벤치마크 회로에 적용하여 실험한 결과 모든 회로에 대하여 향상된 전력소모를 보였다.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.201-206
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• 2007

본 논문에서는 NoC(Network-on Chip) 구조로 구현된 core-based 시스템에 대한 효율적인 저전력 테스트 방법을 제안한다 NoC의 라우터 채널로 전송되는 테스트 데이터의 전력소모를 줄이기 위해서 스캔 벡터들을 채널 폭만큼의 길이를 갖는 flit으로 분할하고 nit간 천이율(switching rate)이 최소화 되도록 don't care 입력을 할당하였다. ISCAS 89 벤치마크에 대하여 실험을 한 결과, 제안된 방법은 약 35%의 전력 감소를 나타내었다.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.156-158
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• 2006

A super-regenerative receiver is designed and tested at 433 MHz ISM band, The designed receiver has the data rate of up to 200 kbps and a power consumption of 10 mW. We carried out the system performance test for the TX power of 0.1 mW and 1 m distance. The result of the bit-error rate test shows one bit error among the 4000 bits.

• 대한물리치료과학회지
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• 제10권1호
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• pp.180-189
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• 2003

The experiments were designated to evaluate the anti-nociceptive effect of low power laser stimulation on acupoint or non-acupoint using arthrogenic solution induced poly arthritis animal model. Evaluation of potential antinociceptive effect of low power laser on arthritis has employed measurements of the foot bending test, the development of either thermal or mechanical hyperalgesia following the arthritis induction. The analysis of thermal hyperalgesia includes Hargreaves's method. Randall-Sellitto test was utilized for evaluating mechanical hyperalgesia. In addition, the antinociceptive effect of low power laser stimulation on arthritis induced spinal Fos expression was analyzed using a computerized image analysis system. The results were summerized as follows: 1. In laser stimulation on acupoint treated animal, laser stimulation dramatically inhibited the development of pain in foot bending test as compared to those of non acupoint treated animal group and non treated animal group. 2. The threshold of thermal stimulation was significantly increased by low power laser stimulation on acupoint as compared to that of non treated control group. 3. Laser stimulation on acupoint dramatically attenuated the development of mechanical hyperalgesia as compared to that of non treated group. 4. Low power laser stimulation on acupoint significantly suppressed arthritis induced Fos expression in the lumbar spinal cord at 3 week post arthritis induction. In conclusion, the results of the present study demonstrated that low power laser stimulation on acupoint has potent anti-nociceptive effect on arthritis. Additional supporting data for an antinociceptive effect of laser stimulation was obtained using Fos immunohistochemical analysis on spinal cord section. Those data indicated that laser stimulation induced antinociception was mediated by suppression of spinal neuron activity in pain sensation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.