• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of Sensor Science and Technology
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• v.5 no.2
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• pp.29-36
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• 1996

With the three dimensional magnetic field measuring system dealt with in this paper, accurate measurements and analyses of extremely low frequency(ELF) magnetic fields caused by starting and/or operating electric devices and power installations can be conducted. To obtain high performance for lower frequency and spatial components without any distortion, the measuring system is designed as three dimensionally including the multiturn loop-type magnetic field sensors, differential amplifiers and active integrators. As the results of calibration experiments, the frequency response characteristics of the measuring system range from 8[Hz] to about 53[kHz] for each direction of x, y, z axes, and the response sensitivities are 9.54, 9.21, $10.89[mV/{\mu}T]$, respectively. The actual survey experiments by using an oscillating impulse current generator confirm a reliability of the proposed measuring system. Also, through the other experiments by using small-sized induction motors, the magnetic field intensities when starting and steady-state operating mark 15.8, $8.61[{\mu}T]$ as maximum value, respectively. And those intensities decrease steeply according as the measuring distance increases.

• Journal of Korea Multimedia Society
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• v.10 no.10
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• pp.1347-1355
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• 2007

A sensor network is composed of a large number of tiny devices, scattered and deployed in a specified regions. Each sensing device has processing and wireless communication capabilities, which enable it to gather information from the sensing area and to transfer report messages to a base station. The energy-efficient routing paths are established when the base station requests a query, since each node has several characteristics such as low-power, constrained energy, and limited capacity. The established paths are recovered while minimizing the total transmit energy and maximizing the network lifetime when the paths are broken. In this paper, we propose a routing algorithm that each sensor node reports its adjacent link information to the sink node when a sink node broadcasts a query. The sink node manages the total topology and establishes routing paths. This algorithm has a benefit to find an alternative path by reducing the negotiating messages for establishing paths when the established paths are broken. To reduce the overhead of collection information, each node has a link information before reporting to the sink. Because the node recognizes which nodes are adjacent. The proposed algorithm reduces the number of required messages, because sensor nodes receive and report routing messages for establishment at the beginning of configuring routing paths, since each node keeps topology information to establish a routing path, which is useful to report sensing tasks in monitoring environments.

• Journal of KIISE:Information Networking
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• v.31 no.6
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• pp.582-594
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• 2004

In school PC labs or other educational purpose PC labs with a few dozens of PCs, computers are configured in a distributed architecture so that they are set up, maintained and upgraded separately. As an alternative to the distributed architecture, we can consider a thin-client computing environment. In a thin-client computing environment, client side devices provide mainly I/O functions with user friendly GUI and multimedia processing support whereas remote servers called terminal server provide computing power. In order to support many clients in the environment, a cluster of terminal servers can be configured. In this architecture, it is difficult due to the characteristics of terminal session persistence and different pattern of computing usage of users so that the utilization of terminal server resources becomes low. To overcome this disadvantage, we propose an adaptive terminal cluster where terminal servers ,ire partitioned into groups and a terminal server in a light-loaded group can be dynamically reassigned to a heavy-loaded group at run time. The proposed adaptive scheme is compared with a generic terminal service cluster and a group based non-adaptive terminal server cluster. Experimental results show the effectiveness of the proposed scheme.

• Journal of KIISE
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• v.42 no.10
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• pp.1268-1279
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• 2015

In order to manage a large number of devices connected to the Internet of Things (IoT), the Internet Engineering Task Force (IETF) proposed the IPv6 Routing Protocol for Low Power and Lossy Networks (RPL). The route of the RPL network is generated through the use of an Objective Function (OF) that is suitable for the service that is required for the IoT network. Since the route of the RPL network is conventionally simply chosen only by considering the link quality between the nodes, it is sensible to seek an OF that can also provide better Quality of Service (QoS). In previous studies, the end-to-end delay might possibly be sub-optimal because they only deal with problems related to the reduction of energy consumption and not to the link quality on the path to the sink node. In this study, we propose a scheme that reduces the end-to-end delay but also gives full consideration to both the quality on the entire route to the destination and to the expected lifetime of nodes with bottlenecks from heaped traffic. Weighting factors for the proposed scheme are chosen by experiments and the proposed scheme can reduce the end-to-end delay and the energy consumption of previous studies by 20.8% and 10.5%, respectively.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.4
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• pp.409-417
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• 2013

Mu-communication board supported by multi-communication is designed with Atxmega 128A1 which is a low power energy consuming of 8-bit microcontroller. ATxmega128A1 microcontroller consists of 8 UART(Universal asynchronous receiver/transmitter) ports which can be setting appropriate user interface having command line interpreter(CLI) program with each port, 2 kbytes EEPROM, 128 kbytes flash memory, 8 kbytes SRAM. 8 URAT ports are used for the multi communication modem, GPS module, etc. and EEPROM is used for saving a configuration for program running, and flash memory of 128 kbytes is used for storing a Firm Ware, and 8 kbytes SRAM is used for stack, storing memory of global variables while program running. If we uses the hybrid communication of path optimization of VHF, TRS and CDMA to remote control AtoN(aid to navigation), it is able to remove the communication shadow area. Even though there is a shadow area for individual communication method, we can select an optimum communication method. The compatibility of data has been enhanced as using of same data frame per communication devices. For the test, 8640 of data has been collected from the each buoy during 30 days in every 5 minutes and the receiving rate of the data has shown more than 99.4 %.

• Korean Journal of Cognitive Science
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• v.21 no.2
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• pp.309-338
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• 2010

In this paper, we studied the brain-computer interface (BCI). BCIs help severely disabled people to control external devices by analyzing their brain signals evoked from motor imageries. The findings in the field of neurophysiology revealed that the power of $\beta$(14-26 Hz) and $\mu$(8-12 Hz) rhythms decreases or increases in synchrony of the underlying neuronal populations in the sensorymotor cortex when people imagine the movement of their body parts. These are called Event-Related Desynchronization / Synchronization (ERD/ERS), respectively. We implemented a BCI-based mouse interface system which enabled subjects to control a computer mouse cursor into four different directions (e.g., up, down, left, and right) by analyzing brain signal patterns online. Tongue, foot, left-hand, and right-hand motor imageries were utilized to stimulate a human brain. We used a non-invasive EEG which records brain's spontaneous electrical activity over a short period of time by placing electrodes on the scalp. Because of the nature of the EEG signals, i.e., low amplitude and vulnerability to artifacts and noise, it is hard to analyze and classify brain signals measured by EEG directly. In order to overcome these obstacles, we applied statistical machine-learning techniques. We could achieve high performance in the classification of four motor imageries by employing Common Spatial Pattern (CSP) and Linear Discriminant Analysis (LDA) which transformed input EEG signals into a new coordinate system making the variances among different motor imagery signals maximized for easy classification. From the inspection of the topographies of the results, we could also confirm ERD/ERS appeared at different brain areas for different motor imageries showing the correspondence with the anatomical and neurophysiological knowledge.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.97-105
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• 2017

An air-burst munition is limited in space, so there is a limit on the size of the fuze and the amount of ammunition. In order to increase a firepower to a target with limited ammunition, it is necessary to concentrate the firepower on the ground instead of the omnidirectional explosion after flying to the target. This paper explores the design and verification of a ground-detection sensor that detects the direction of the ground and determines the flight-distance of an air-burst munition using a single axis geomagnetic sensor. Prior to the design of the ground detection sensor, a geomagnetic sensor model mounted on the spinning air-burst munition is analyzed and a ground-detection algorithm by simplifying this model is designed. A high speed rotating device to simulate a rotation environment is designed and a geomagnetic sensor and a remote-recording system are fabricated to obtain geomagnetic data. The ground detection algorithm is verified by post-processing the acquired geomagnetic data. Taking miniaturization and low-power into consideration, the ground detection sensor is implemented with analog devices and the processor. The output signal of the ground detection sensor rotating at an arbitrary rotation speed of 200 Hz is connected to the LED (Light Emitting Diode) in the high speed rotating device and the ground detection sensor is verified using a high-speed camera.