• IEMEK Journal of Embedded Systems and Applications
• /
• v.15 no.6
• /
• pp.299-305
• /
• 2020

We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.6 no.10
• /
• pp.2509-2528
• /
• 2012

Time division multiple access (TDMA) is a widely used media access control (MAC) technique that can provide collision-free and reliable communications, save energy and bound the delay of packets. In TDMA, energy saving is usually achieved by switching the nodes' radio off when such nodes are not engaged. However, the frequent switching of the radio's state not only wastes energy, but also increases end-to-end delay. To achieve high energy efficiency and low delay, as well as to further minimize the number of time slots, a multi-objective TDMA scheduling problem for industrial wireless mesh networks is presented. A hybrid algorithm that combines genetic algorithm (GA) and simulated annealing (SA) algorithm is then proposed to solve the TDMA scheduling problem effectively. A number of critical techniques are also adopted to reduce energy consumption and to shorten end-to-end delay further. Simulation results with different kinds of networks demonstrate that the proposed algorithm outperforms traditional scheduling algorithms in terms of addressing the problems of energy consumption and end-to-end delay, thus satisfying the demands of industrial wireless mesh networks.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.12
• /
• pp.680-686
• /
• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.9
• /
• pp.1748-1753
• /
• 2011

In this paper, we consider the stability of linear systems with an interval time-varying delay. It is known that the adoption of decomposition of delay improves the stability result. For the interval time-delay case, they applied it to the interval of time-delay and got less conservative results. Our basic idea is to apply the general decomposition to the low limit of delay as well as interval of time-delay. Based on this idea, by using the modified Lyapunov-Krasovskii functional and newly derived Lemma, we present a less conservative stability criterion expressed as in the form of linear matrix inequality(LMI). Finally, we show, by well-known two examples, that our result is less conservative than the recent results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.2
• /
• pp.144-149
• /
• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.457-462
• /
• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.727-730
• /
• 2005

In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

• Journal of electromagnetic engineering and science
• /
• v.3 no.1
• /
• pp.62-66
• /
• 2003

Novel coupled line phase shifters and its equivalent phase delay line for compact broadband phased array antennas are proposed. These phase control circuits are designed to be less complex, small size and to use a less number of active devices. The phase shifter is able to control a 120$^{\circ}$ phase shift continuously, and the phase delay line for a reference phase has a fixed 60$^{\circ}$ shifted phase. Both have the low phase error of less than $\pm$3.5$^{\circ}$ and the low gain variations of less than 1 ㏈ within the 300 MHz bandwidth. These proposed circuits are adequate to form the efficient beam-forming networks with compactness, broadband, less complexity, and low cost.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2006.11a
• /
• pp.903-908
• /
• 2006

As environmental vibration requirements on precision equipment become more stringent. use of pneumatic isolators has become more popular and their performance is subsequently required to be further improved. Dynamic performance of passive pneumatic isolators is related to various design parameters in a complicated manner and, hence, is very limited especially in low frequency range by volume of chambers. In this study, an active control technique, so called time delay control which is considered to be adequate for a low frequency or nonlinear system, is applied to a single chamber pneumatic isolator. The procedure of applying the time delay control law to the pneumatic isolator is presented and its effectiveness in enhancement of transmissibility performance is shown based on simulation and experiment. Comparison between passive and active pneumatic isolators is also presented.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.5
• /
• pp.303-309
• /
• 2016

This paper presents a channel-adaptive rate control algorithm for low delay video coding. The main goal of the proposed method is to adaptively use the unknown available channel bandwidth while reducing the end-to-end delay between encoder and decoder. The key idea of the proposed algorithm is for the status of the encoder buffer to indirectly reflect the mismatch between the available channel bandwidth and the generated bitrate. Hence, the proposed method fully utilizes the unknown available channel bandwidth by monitoring the encoder buffer status. Simulation results show that although the target bitrate mismatches the available channel bandwidth, the encoder efficiently adapts the given available bandwidth to improve the peak signal-to-noise ratio.